EP7211 Datasheet, PDF (35/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
• On-chip Boot ROM programmed with serial load boot sequence
• Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level greyscaler
• Programmable frame buffer start address, allowing a system to be built using only external or
internal SRAM for memory, eliminating any need for DRAMs at all
• Two full duplex 16C550 style UARTs with two 16-byte FIFOs
• IrDA SIR Protocol controller capable of speeds up to 115.2 kbps
• Two 16-bit general purpose timer counters
• A 32-bit real time clock and comparator
• Dedicated LED flasher pin driven from the RTC with programmable duty ratio
• Two PWM interfaces
• Advanced system state control and power management
• Two synchronous serial interfaces for Microwire or SPI peripherals such as ADCs, one
supporting both the master and slave mode and up to 512 kbps continuous data rate, while the
other supports only the master mode with no buffering, and up to 128 kbps
• Full boundary scan — JTAG
• External tracing support for debug
• The main oscillator and phase locked loop (PLL) to generate twice the maximum CPU clock of
73.728 MHz from a 3.6864 MHz crystal, with an alternative external clock input (used in 13
MHz mode)
• A low power 32.768 kHz oscillator
Figure 3-1. EP7211 Block Diagram shows a simplified block diagram of the EP7211. All external
memory and peripheral devices are connected to the 32-bit data bus using the external 28-bit address
bus and control signals. Bus transfer times can be extended using the EXPRDY signal to lengthen
bus cycles.
DS352PP3
JUL 2001
35
Functional Description