EP7211 Datasheet, PDF (120/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-13. MCP Control Register (cont.)
Bit
20
21
22
23
31–24
Name
TRM
ATM
ARM
LBM
—
Description
Telecom Receive FIFO Interrupt Mask
0 — Telecom receive FIFO half-full or more condition does not generate an interrupt (TRS bit ignored).
1 — Telecom receive FIFO half-full or more condition generates an interrupt (state of TRS sent to inter-
rupt controller).
Audio Transmit FIFO Interrupt Mask
0 — Audio transmit FIFO half-full or less condition does not generate an interrupt (ATS bit ignored).
1 — Audio transmit FIFO half-full or less condition generates an interrupt (state of ATS sent to interrupt
controller).
Audio Receive FIFO Interrupt Mask
0 — Audio receive FIFO half-full or more condition does not generate an interrupt (ARS bit ignored).
1 — Audio receive FIFO half-full or more condition generates an interrupt (state of ARS sent to inter-
rupt controller).
Loop Back Mode
0 — Normal serial port operation enabled
1 — Output of serial shifter is connected to input of serial shifter internally and control of SIBDIN, SIBD-
OUT, SCLK, and SIBSYNC pins is given to the PPC unit.
Reserved
5.16.2 MCP Data Registers
The MCP contains three data registers: MCDR0 addresses the top entry of the audio transmit FIFO
and bottom entry of the audio receive FIFO; MCDR1 addresses the top and bottom entry of the
telecom transmit and receive FIFOs, respectively; and MCDR2 is used to perform reads and writes
to any of the codec’s sixteen registers via the MCP’s serial interface.
5.16.2.1 MCP Data Register 0
ADDRESS: 0x8000.2040
When MPC Data Register 0 (MCDR0) is read, the bottom entry of the audio receive FIFO is
accessed. As data is removed by the MCP’s receive logic from the incoming data frame, it is placed
into the top entry of the audio receive FIFO and is transferred down an entry at a time until it reaches
the last empty location within the FIFO. Data is removed by reading MCDR0, which accesses the
bottom entry of the audio FIFO. After MCDR0 is read, the bottom entry is invalidated, and all
remaining values within the FIFO automatically transfer down one location.
When MCDR0 is written, the top-most entry of the audio transmit FIFO is accessed. After a write,
data is automatically transferred down to the lowest location within the transmit FIFO which does
not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by
the transmit logic, is loaded into the correct position within the 64-bit transmit serial shifter, then
serially shifted out onto the SIBDOUT pin during subframe 0.
Audio data is 12-bits wide and must be left justified by the user before writing them to the transmit
FIFO (MSB of audio data corresponds to bit 16 of transmit FIFO). The lower four bits of the FIFO
which are aligned within the 16-bit value are also written to MCDR0 for transmission. Nevertheless,
120
Register Descriptions
DS352PP3
JUL 2001