EP7211 Datasheet, PDF (151/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Oscillator and PLL Test Mode Signals defines the EP7211 signal pins used in this test mode. This
mode is only intended to allow test of the oscillators and PLL.
Table 7-2. Oscillator and PLL Test Mode Signals
Signal
TSEL *
XTLON *
PLLON *
PLLBP
RTCCLK
CLK1
OSC36
CLK576K
VREF
I/O
Pin
Function
I
PA5
PLL test mode
I
PA4
Enable to oscillator circuit
I
PA3
Enable to PLL circuit
I
PA0
Bypasses PLL
O
COL0 Output of RTC oscillator
O
COL1 1 Hz clock from RTC divider chain
O
COL2 36 MHz divided PLL main clock
O
COL4 576 KHz divided from above
O
COL6 Test clock output for PLL
Note that these inputs are inverted before being passed to the PLL to ensure that the default state of
the port (all zero) maps onto the correct default state of the PLL (TSEL = 1, XTALON = 1, PLLON
= 1, D0 = 0, D1 = 1, PLLBP = 0). This state will produce the correct frequencies as shown in Table
7-2. Oscillator and PLL Test Mode Signals. Any other combinations are for testing the oscillator
and PLL and should not be used in-circuit.
7.3 Debug/ICE Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 1.
Selection of this mode enables the debug mode of the ARM720T. By default, this is disabled which
saves approximately 3% on power.
7.4 Hi-Z (System) Test Mode
This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0.
This test mode asynchronously disables all output buffers on the EP7211. This has the effect of
removing the EP7211 from the PCB so that other devices on the PCB can be in-circuit tested. The
internal state of the EP7211is not altered directly by this test mode.
7.5 Software Selectable Test Functionality
When Bit 11 of the SYSCON register is set high, internal peripheral bus register accesses are output
on the main address and data buses as though they were external accesses to the address space
addressed by CS5. Hence, CS5 takes on a dual role, it will be active as the strobe for internal accesses
and for any accesses to the standard address range for CS5. Additionally, in this mode, the internal
DS352PP3
JUL 2001
151
Test Modes