EP7211 Datasheet, PDF (115/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.1 MCP Control Register
ADDRESS: 0x8000.2000
The MCP control register (MCCR) contains ten different bit fields that control various functions
within the MCP.
5.16.1.1 Audio Sample Rate Divisor (ASD)
The 7-bit audio sample rate divisor (ASD) bit field is used to synchronize the MCP with the sample
rate of the audio codec. Sample rate synchronization is required such that the MCP’s audio transmit
FIFO logic knows when to load a new value for D/A conversion to the MCP’s serial shifter for
transmission. This field is programmed with the same value that is written to the codec’s sample rate
divisor via a codec control register write. When the audio codec is enabled, the first audio transmit
value is placed in the serial output stream by the transmit FIFO, and both the MCP’s and codec’s
sample rate counters begin to decrement in lock-step with one another. When the audio codec’s
counter decrements to zero, it uses the value transmitted to it by the MCP to perform the D/A
conversion. After the conversion is made, the MCP and codec’s counters reset to their modulus
value, and the MCP’s audio transmit FIFO loads the next value to the MCP’s serial shifter for
transmission. This new value is then transmitted to the audio codec and is used for the next D/A
conversion, which is signaled when the sample rate counter decrements to zero again.
In principle, a total of 122 different audio sample rates can be selected, ranging from a minimum of
2.953 K samples per second to a maximum of 62.5 K samples per second (for a range of ASD values
between 6 (00000110) and 127 (11111111)). The sample rate clock generator uses the 9.216 MHz
(6.5 MHz for 13MHz mode) MCP clock, generated from a division of the chip’s clock by 4, which
in turn is divided by a fixed value of 32 and then the programmable ASD value to generate the audio
sample clock, inside the CODEC.
For instance, for the Philips UCB1100 the sampling clock is automatically enabled when:
A codec control register write to the audio control register B is made (address=’1000’) which sets
either the audio codec input or output enable bits (Bit 14 = aud_in_ena, Bit 15 = aud_out_ena) of this
register, followed by the rising edge of the next SIBSYNC pulse, after the write has been made
Once enabled, the MCP’s audio sample rate counter decrements at the programmed frequency with
a 50% duty cycle. The particular, the codec control register write outlined above causes the MCP’s
audio transmit FIFO logic to transfer the next available value to the audio data field within the serial
shifter. Each time the audio sample rate counter decrements to zero, it is reloaded with its
programmed ASD modulus value, triggers the audio transmit FIFO logic to transfer the next
available value to the audio data field within the serial shifter, and continues to decrement.
Again, taking the example of the UCB1100 codec, the MCP’s audio sample rate clock is
automatically disabled when: a codec control register write to the codec audio control register B is
made (address=’1000’) which clears both the audio codec input and output enable bits (bit 14 =
aud_in_ena, bit 15 = aud_out_ena), followed by the rising edge of the next SIBSYNC pulse after the
write has been made. The resulting audio sample clock rate, given a specific ASD value can be
DS352PP3
JUL 2001
115
Register Descriptions