EP7211 Datasheet, PDF (152/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
signals shown in Table 7-3. Software Selectable Test Functionality are multiplexed out of the
device on port pins.
Table 7-3. Software Selectable Test Functionality
Signal
CLK
NFIQ
NIRQ
I/O
Pin
Function
O
PE0
Waited clock to CPU
O
PE1
NFIQ interrupt to CPU
O
PE2
NIRQ interrupt to CPU
This test is not intended to be used when LCD DMA accesses are enabled. This is due to the fact that
it is possible to have internal peripheral bus activity simultaneously with a DMA transfer. This would
cause bus contention to occur on the external bus.
The ‘Waited clock to CPU’ is an internally ANDed source that generates the actual CPU clock. Thus,
it is possible to know exactly when the CPU is being clocked by viewing this pin.
The signals NFIQ and NIRQ are the two output signals from the internal interrupt controller. They
are input directly into the ARM720T processor.
152
Test Modes
DS352PP3
JUL 2001