EP7211 Datasheet, PDF (34/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
• Critical program storage
• LCD frame buffer
• General purpose data storage
The EP7211 supports a number of serial interface protocols including two high speed (115 kbps)
UARTs with RX and TX FIFOs, a codec interface with FIFO support, and two additional
synchronous serial interfaces. One of the UARTs also supports the IrDA SIR protocol.
The EP7211 also has an on-chip Boot ROM (128 bytes), which is hardware selectable on power-on
reset. This Boot ROM initializes UART1, and downloads the application-specific main boot code
into the on-chip SRAM. Once download is complete, execution jumps to the start of the on-chip
SRAM. This feature could be used in a manufacturing environment to allow the EP7211 to download
code into on-board blank Flash. [See Section 10 Appendix A: Boot Code on page 157]
The EP7211 design is optimized for low power dissipation, and is fabricated on a fully static 0.25
micron CMOS process. It is available in 256-ball PBGA and 208-pin LQFP packages.
3.1 Main Functional Blocks
The principle functional blocks in the EP7211 are:
• ARM720T processor, which consists of the following functional sub-blocks:
– ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced
multiplier, JTAG, and the Embedded ICE)
– Memory management unit from the ARM700 and ARM710 processors with WinCE support; it also contains a
64-bit translation look aside buffer (TLB)
– 8 kbytes of unified instruction and data cache, four-way set associative cache controller
– Write buffer
• 38,400 bytes of SRAM; full address decode is performed.
• Two PC Card slots supported by an interface to one CL-PS6700 per slot
• Interrupt controller
• Expansion and ROM/SRAM/Flash interface giving 4, 5, or 6 x 256 Mbyte expansion segments
with independent wait states
• DRAM controller supporting EDO, fast page and self-refresh in the Standby State, and both 16-
bit and 32-bit wide memory (Fast Page DRAM is only supported at 13 MHz and 18 MHz
• 27 bits of general purpose peripheral I/O — multiplexed to provide additional functionality
where necessary
• Codec sound interface with 16-byte transmit and receive FIFOs
• MCP (Multimedia Codec Port) giving access to an audio codec, a telecom codec, a touchscreen
interface, four general purpose analog-to-digital converter inputs, and ten programmable digital
I/O lines
34
Functional Description
DS352PP3
JUL 2001