EP7211 Datasheet, PDF (19/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2
(Section 5.2.2 SYSCON2 System Control Register 2). The choice between the SSI2, codec, and
the MCP is controlled by the MCPSEL bit in SYSCON3 (Section 5.2.3 SYSCON3 System Control
Register 3).
NOTE: All deglitched inputs are via the 16.384 kHz clock. Therefore, the input signal must be active for at
least ~61 µs to be detected cleanly.
The following output pins are implemented as bi-directional pins to enable the output side of the pad
to be monitored and hence provide more accurate control of timing or duration:
RUN
The RUN pin is looped back in to skew the address and data bus from each other.
NCAS[3:0]
The NCAS pins are looped back into the EP7211 to be used as the actual clock
source for the data to be latched internally.
Drive 0 and 1 Drive 0 and 1 are looped back in on power up to determine what polarity the output
of the PWM should be when active.
DD[3:0]
DD[3:0] are looped back in on power up to enable the reading of the ID of some
LCD modules.
DS352PP3
JUL 2001
19
Pin Information