EP7211 Datasheet, PDF (110/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-12. Grey Scale Value to Color Mapping (cont.)
Grey Scale Value
8
9
10
11
12
13
14
15
Duty Cycle
1/2
5/9
3/5
6/9
11/15
4/5
8/9
1
% Pixels Lit
50.0 %
55.6 %
60.0 %
66.7 %
73.3 %
80.0 %
88.9 %
100 %
% Step Change
5.6 %
5.4 %
6.7 %
6.6 %
6.7 %
8.9 %
11.1 %
5.10.4 FBADDR LCD Frame Buffer Start Address
ADDRESS: 0x8000.1000
This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer
starts at location 0x0000000 within each chip select memory region. Therefore, the value stored
within the FBADDR register is only the value of the chip select where the frame buffer is located).
On reset, this will be set to 0xC for backward compatibility with the CL-PS7111. Thus the frame
buffer defaults to the start of DRAM Bank 0. The register is 4 bits wide (bits [3:0]). This register
must only be reprogrammed when the LCD is disabled (i.e., setting the LCDEN bit within
SYSCON2 low).
5.11 SSI Register
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register
ADDRESS: a0x8000.0500
SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the
master only SSI. In default mode, the least significant byte is serialized and transmitted out of the
synchronous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended
mode, a variable number of bits are sent from SYNCIO[31:16] as determined by the ADC
Configuration Length. The transfer clock will automatically be started at the programmed frequency
and a synchronization pulse will be issued. The ADCIN pin is sampled on every positive going clock
edge (or the falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to
the SYNCIO read register.
During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will
be asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the
SYNCIO register is the last sixteen bits shifted out of the ADC.
110
Register Descriptions
DS352PP3
JUL 2001