EP7211 Datasheet, PDF (43/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-6. Chip Select Address Ranges After Boot From On-Chip Boot ROM (cont.)
Address Range
5000.0000–5FFF.FFFF
6000.0000–6FFF.FFFF
7000.0000–7FFF.FFFF
Chip Select
NCS2
NCS1
NCS0
3.6 CL-PS6700 PC Card Controller Interface
Two of the expansion memory areas are dedicated to supporting up to two CL-PS6700 PC Card
controller devices. These are selected by NCS4 and NCS5 (once enabled by bits 5 and 6 of
SYSCON2). For efficient, low power operation, both address and data are carried on the lower 16
bits of the EP7211 data bus. Accesses are initiated by a write or read to or from the area of memory
allocated for NCS4 or NCS5. The memory map within each of these areas is segmented to allow
different types of PC Card accesses to take place, for attribute, I/O, and common memory space. The
CL-PS6700 internal registers are memory mapped within the address space as shown in Table 3-7.
CL-PS6700 Memory Map.
NOTE: It must be noted that, due to the operating speed of the CL-PS6700, this interface is supported only
for processor speeds of 13 and 18 MHz.
Access Type
Attribute
I/O
Common memory
CL-PS6700 registers
Table 3-7. CL-PS6700 Memory Map
Addresses for CL-PS6700 Interface 1 Addresses for CL-PS6700 Interface 2
0x40000000–0x43FFFFFF
0x50000000– 0x53FFFFFF
0x44000000–0x47FFFFFF
0x54000000–0x57FFFFFF
0x48000000–0x4BFFFFFF
0x58000000–0x5BFFFFFF
0x4C000000–0x4FFFFFFF
0x5C000000–0x5FFFFFFF
A complete description of the protocol and AC timing characteristics can be found in the CL-PS6700
Databook. A transaction is initiated by an access to the NCS4 or NCS5 area. The chip select is
asserted, and on the first clock, the upper 10 bits of the PC Card address, along with 6 bits of size,
space, and slot information are put out onto the lower 16 bits of the EP7211’s data bus. Only word
(i.e., 4-byte) and single-byte accesses are supported, and the slot field is hardcoded to 11, since the
slot field is defined as a ‘Reserved field’ by the CL-PS6700. The chip selects are used to select the
device to be accessed. The space field is made directly from the A26 and A27 CPU address bits,
according to the decode shown in Table 3-8. Space Field Decoding below. The size field is forced
to 11 if a word access is required, or 00 if a byte access is required. This avoids the need to configure
the interface after a reset. On the second clock cycle, the remaining 16 bits of the PC Card address
are multiplexed out onto the lower 16 bits of the data bus. If the transaction selected is a CL-PS6700
register transaction, or a write to the PC Card (assuming there is space available in the CL-PS6700’s
DS352PP3
JUL 2001
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Functional Description