EP7211 Datasheet, PDF (51/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
3.8.1 Codec Sound Interface
The codec interface allows direct connection of a telephony type codec to the EP7211. It provides
all the necessary clocks and timing pulses and performs a parallel to serial conversion or vice versa
on the data stream to or from the external codec device. The interface is full duplex and contains two
separate data FIFOs (16 deep by 8-bits wide, one for the receive data, another for the transmit data).
Data is transferred to or from the codec at 64 kbps. The data is either written to or read from the
appropriate 16 byte FIFO. If enabled, a codec interrupt (CSINT) will be generated after every 8 bytes
are transferred (FIFO half full/empty). This means the interrupt rate will be every 1 ms, with a
latency of 1 ms.
Transmit and receive modes are enabled by asserting high both the CDENRX and CDENTX codec
enable bits in the SYSCON1 register.
NOTE: Both the CDENRX and CDENTX enable bits should be asserted in tandem for data to be transmitted
or received. The reason for this is that the interrupt generation will occur 1 ms after one of the FIFOs
is enabled. For example: If the receive FIFO gets enabled first and the transmit FIFO at a later time,
the interrupt will occur 1 ms after the receive FIFO is enabled. After the first interrupt occurs, the
receive FIFO will be half full. However, it will not be possible to know how full the transmit FIFO will
be since it was enabled at a later time. Thus, it is possible to unintentionally overwrite data already in
the transmit FIFO. See the following diagram:
CDENRX
CDENTX
CSINT
1 ms
1 ms
1 ms
Figure 3-2. Codec Interrupt Timing
3.8.1.1 Codec Interrupt Timing
After the CDENRX and CDENTX enable bits get asserted, the corresponding FIFOs become
enabled. When deasserted low, the FIFO status flags (i.e., CRXFE and CTXFF located in the
SYSFLAG register) are cleared and the FIFOs appear empty. Additionally, if the CDENTX bit is
low, the PCMOUT output is disabled. Asserting either of the two enable bits causes the sync and
interrupt generation logic to become active; otherwise they are disabled to conserve power.
DS352PP3
JUL 2001
51
Functional Description