EP7211 Datasheet, PDF(37/166 Page) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

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EP7211 Datasheet, PDF (37/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

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EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

than IRQs. If two interrupts within the same group (IRQ or FIQ) are active, the order in which they

are serviced must be resolved in software.

All interrupts are level sensitive; that is, they must conform to the following sequence.

1) The interrupting device (either external or internal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask register, then either a FIQ or an IRQ will be as-

serted by the interrupt controller. (A description for each bit in this register can be found in Sec-

tion 5.3.1 INTSR1 Interrupt Status Register 1 on page 94.)

3) If interrupts are enabled the processor will jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the in-

terrupt and calls the appropriate interrupt service routine(s).

5) Software in the interrupt service routine will clear the interrupt source by some action specific to

the device requesting the interrupt (e.g., reading the UART RX register).

The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be

serviced in a similar way. Alternately, it may return to the interrupt dispatch code, which can check

for any more pending interrupts and dispatch them accordingly. The âEnd of Interruptâ type

interrupts are latched. All other interrupt sources (e.g., external interrupt source) must be held active

until its respective service routine starts executing. See Section 5.13 for more details.

Table 3-1, Table 3-2 and Table 3-3 show the names and allocation of interrupts in the EP7211.

Table 3-1. Interrupt Allocation in First Interrupt Register

Interrupt

FIQ

IRQ

Bit in INTMR1

and INTSR1

Name

EXTFIQ

BLINT

WEINT

MCINT

CSINT

EINT1

EINT2

EINT3

TC1OI

TC2OI

RTCMI

TINT

Comment

External fast interrupt input (NEXTFIQ pin)

Battery low interrupt

Watchdog expired interrupt

Media changed interrupt

Codec sound interrupt

External interrupt input 1 (NEINT1 pin)

External interrupt input 2 (NEINT2 pin)

External interrupt input 3 (EINT3 pin)

TC1 underflow interrupt

TC2 underflow interrupt

RTC compare match interrupt

64 Hz tick interrupt

DS352PP3

JUL 2001

Functional Description

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