EP7211 Datasheet, PDF (70/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
NOTE: The CPU cannot be awakened by the TINT, WEINT, and BLINT interrupts when in the Standby State.
Typically, software writes to the Standby internal memory location to cause the transition from the
Operating State to the Standby State. Before entering the Standby State, if external I/O devices (such
as the CL-PS6700s connected to NCS[4] or NCS[5]) are in use, the software must check to ensure
that they are idle before issuing the write to the Standby State location.
Before entering the Standby State, the software must properly disable the MCP. Failing to do so will
result in higher than expected power consumption in the Standby State, as well as unpredictable
operation of the MCP. The MCP can be re-enabled after transitioning back to the Operating State.
The system can also be forced into the Standby State by hardware if the NPWRFL or NURESET
inputs are forced low. In this case the transition is synchronized with DRAM cycles to avoid any
glitches or short cycles.
The only exit from the Standby State is to the Operating State.
The system will only transition to the Operating State from the Standby State under the following
conditions: when the NPWRFL input pin is high and either the NEXTPWR input pin is low or the
BATOK input pin is high. This prevents the system from starting when the power supply is
inadequate (e.g., the main batteries are low), corresponding to a low level on NPWRFL or BATOK.
From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock
running, the EP7211 will be initialized into a state where it is ready to start and is waiting for the
CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock
is applied, there will be a delay of about eight clock cycles before the CPU is first clocked. This is to
allow the clock to the CPU to settle.
During the Standby State, the UARTs are disabled and cannot detect any activity (e.g., start bit) on
the receiver. If this functionality is required then this can be accomplished in software by the
following method:
1) Permanently connect the RX pin to one of the active low external interrupt pins.
2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the
UART is enabled.
3) Send a preamble that consists of one start bit, 8-bits of zero, and one stop bit. This will cause the
EP7211 to wake and execute the enabled interrupt vector.
The UART will automatically be re-enabled when the processor re-enters the Operating State, and
the preamble will be received. Since the UART was not awake at the start of the preamble, the timing
of the sample point will be off-center during the preamble byte. However, the next byte transmitted
will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured
correctly.
If in the Operating State, the Idle State can be entered by writing to a special internal memory
location in the EP7211. If an interrupt or wakeup event occurs, the EP7211 will return immediately
back to the Operating Stateand execute the next instruction.
70
Functional Description
DS352PP3
JUL 2001