EP7211 Datasheet, PDF (5/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
TABLE OF CONTENTS
1. CONVENTIONS........................................................................................................................11
1.1 Acronyms and Abbreviations................................................................................................................... 11
1.2 Units of Measurement .............................................................................................................................12
1.3 General Conventions...............................................................................................................................12
1.4 Pin Description Conventions ...................................................................................................................12
2. PIN INFORMATION..................................................................................................................13
2.1 Pin Diagrams...........................................................................................................................................13
2.2 Pin Descriptions ......................................................................................................................................14
2.2.1 External Signal Functions...........................................................................................................15
2.3 256-Ball PBGA Ball Listing......................................................................................................................20
2.3.1 PBGA Ground Connections .......................................................................................................25
2.4 208-Pin LQFP Pin Listing ........................................................................................................................26
2.5 JTAG Pin Ordering for 208-Pin LQFP Package ......................................................................................31
3. FUNCTIONAL DESCRIPTION.................................................................................................34
3.1 Main Functional Blocks ...........................................................................................................................35
3.2 CPU Core ................................................................................................................................................37
3.3 Interrupt Controller ..................................................................................................................................37
3.3.1 Interrupt Latencies in Different States ........................................................................................39
3.3.1.1 Operating State ..........................................................................................................39
3.3.1.2 Idle State ....................................................................................................................40
3.3.1.3 Standby State .............................................................................................................40
3.4 Memory and I/O Expansion Interface ......................................................................................................42
3.5 EP7211 Boot ROM ..................................................................................................................................43
3.6 CL-PS6700 PC Card Controller Interface ...............................................................................................44
3.7 DRAM Controller with EDO Support .......................................................................................................47
3.8 Serial Interfaces ......................................................................................................................................51
3.8.1 Codec Sound Interface...............................................................................................................52
3.8.1.1 Codec Interrupt Timing...............................................................................................52
3.8.2 MCP Interface ............................................................................................................................53
3.8.2.1 MCP Operation ..........................................................................................................54
3.8.2.2 MCP Frame Format ...................................................................................................54
3.8.2.3 Audio and Telecom Sample Rates and Data Transfer ...............................................56
3.8.2.4 MCP FIFO Operation .................................................................................................58
3.8.2.5 MCP Codec Control Register Data Transfer ..............................................................59
3.8.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) ...............................60
3.8.4 Master/Slave SSI2 (Synchronous Serial Interface 2) .................................................................61
3.8.4.1 Read Back of Residual Data ......................................................................................62
3.8.4.2 Support for Asymmetric Traffic ...................................................................................63
3.8.4.3 Continuous Data Transfer ..........................................................................................63
3.8.4.4 Discontinuous Clock...................................................................................................63
3.8.4.5 Error Conditions .........................................................................................................64
3.8.4.6 Clock Polarity .............................................................................................................64
3.9 LCD Controller with Support for On-Chip Frame Buffer ..........................................................................64
3.10 Internal UARTs (Two) and SIR Encoder ..................................................................................................67
3.11 Timer Counters........................................................................................................................................67
3.11.1 Free Running Mode....................................................................................................................68
DS352PP3
5
JUL 2001