EP7211 Datasheet, PDF (52/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Data is loaded into the transmit FIFO by writing to the CODR register. At the beginning of a transmit
cycle, this data is loaded into a shift/load register. Just prior to the byte being transferred out,
PCMSYNC goes high for one PCMCLK cycle. Then the data is shifted out serially to PCMOUT,
MSB first, (with the MSB valid at the same time PCMSYNC is asserted). Data is shifted on the rising
edge of the PCMCLK output.
Receiving of data is performed by taking data in serially through PCMIN, again MSB first, shifting
it through the shift/load register and loading the complete byte into the receive FIFO. Input data is
sampled on the falling edge of PCMCLK. Data is read from the CODR register.
NOTE: After data is transmitted, the speaker amplifier should be turned off to avoid audible noise. This is
needed because the EP7211 will continue to transmit data from the FIFO even though it is empty, thus
causing noise. This will occur even when receiving.
3.8.2 MCP Interface
The Multimedia Communications Port (MCP) provides an interface to the Philips UCB1100 codec.
This device has an audio codec, a telecom codec, a touch-screen interface, four general purpose ADC
inputs, and ten programmable digital I/O lines. The MCP interface is used by the device both to input
and output digital data to and from the codec, and to configure and acquire status information from
the codec’s 16 registers.
The MCP produces two 64-bit subframes per frame (128 bits for both subframes in the frame) using
a bit clock and frame synchronization signal. Data is communicated full duplex via a separate
transmit and receive data line. The bit clock frequency is fixed at 9.216 Mbps for all modes except
the 13 MHz mode. For the 13 MHz mode, the bit clock frequency is fixed at 6.5 Mbps. The MCP
communicates to the codec in the first of the two subframes. The second subframe is used in high-
end applications to communicate with a second stereo codec, such as Crystal’s CS4216/18, however
this feature is not supported by the MCP. Each 64-bit subframe contains seven different fields of
information. These fields include audio conversion data, telecom conversion data, data valid flags,
control register address, control register data, and read/write control. Both transmit and receive data
contains these seven fields. The transmitted frame contains data for D-to-A conversion, as well as
address, data, and control signals to write to or read from the codec’s registers. The received frame
contains A-to-D samples, and the data returned from a read of a codec register.
Both the MCP and the off-chip codec contain programmable 7-bit divisors, one each for the telecom
and audio data. These values are used to divide the bit clock to generate a desired sampling
frequency. When the codec is enabled, the divisor pairs are synchronously transferred to their
respective modulus registers within the MCP and codec’ and decrement using the bit clock. This
technique allows telecom and audio data to be transferred between the MPC and codec, lock-step in
sync with the sampling/conversion frequency of the codec.
The MCP contains two pairs of transmit FIFOs and two pairs of receive FIFOs, one each for audio
and telecom data. In the current implementation, the two receive FIFOs are deeper than the two
transmit FIFOs. The sizes of the audio/telecom transmit FIFOs are 8 x 16-bit words and of the
audio/telecom receive FIFOs are 12 x 16-bit words. The MCP also contains a 21-bit data register used
to transmit codec register reads and writes, as well as another 21-bit register to receive the results of
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Functional Description
DS352PP3
JUL 2001