EP7211 Datasheet, PDF (54/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit 63
48 47 46
43 42 41
34 33 32 31
16 15
0
TX Audio Transmit Data 0 Address
R/ 00000000
W
AV T Telecom Transmit Data Control
V
Register Write
RX Audio Receive Data
0 Address
R/ 00000000
W
AV T Telecom Receive Data
V
Control
Register Read
NOTE: AV – Audio Data Valid, TV – Telecom Data Valid, R/W – write=1 read=0, Address -– codec register
address
Figure 3-3. Data Format of MCP Subframe 0
Both the MCP and the off-chip codec drive data on the rising-edge of SIBCLK and latch data on its
falling-edge. After SIBSYNC is negated, subframe 0 begins and the data within the 64-bit shifter is
driven onto the SIBDOUT pin a bit at a time, starting with MSB[63]. As each bit of data is shifted
onto the SIBDOUT pin from one side of the shifter, a bit is also shifted into the opposite end of the
shifter from the SIBDIN pin. After 64 SIBCLK cycles elapse, all data within the shifter has been
transmitted, and the shifter contains the 64-bit receive data frame. The MCP takes the data from each
field and places it in its respective receive FIFO or data register. The next 64 SIBCLK cycles make
up subframe 1. When subframe 1 is active, the clocks to all MCP resources, which are not needed,
are turned off in order to conserve power. Table 3-4 shows the pin timing of the MCP.
Frame Clock Count 1
2
... 63
64
65
66
... 127
128
1
Frame N
Frame N+1
Subframe
Subframe 0
Subframe 1
SIBCLK
...
...
SIBSYNC
...
SIBDOUT
[63]
[62]
... [1] [0]
[63]
...
[0]
[63]
SIBDIN
[63]
[62]
... [1]
Bit
[63]
...
Figure 3-4. MCP Packet Organization
[0]
[63]
54
Functional Description
DS352PP3
JUL 2001