EP7211 Datasheet, PDF (145/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
DRA[12:0]
RAS[3:0]
CAS[3:0]
Held
W_&6$
W_5$6 ^W5&
Row
Col
D[31:0]
Held
NMOE
NMWE
Figure 6-10. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz
NOTES:
1). t_CSA (CAS set-up time) = 15 ns max at 18.432 MHz and 20 ns at 13 MHz
2) t_RAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
3) t_RC (cycle time) = 180 ns max at 18.432 MHz and 230 ns at 13 MHz
When DRAMs are placed in self-refresh (entering the Standby State), the same timings, except that
t_RAS is extended indefinitely.
4) The filled-in grey area is a don’t care.
DS352PP3
JUL 2001
145
Electrical Specifications