EP7211 Datasheet, PDF (71/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
In the Idle State, the device functions just like it does when in the Operating State. However, the CPU
clock is halted while it waits for an event such as a key press to generate an interrupt, or a rising edge
on the external WAKEUP pin. The PLL (in 18.432–73.728 MHz mode) or the external 13 MHz
clock source always remains active in the Idle State.
Figure 3-10. State Diagram shows a state diagram for the EP7211.
Standby
Interrupt or rising wakeup
Write to standby location,
power fail, or user reset
Operating
NPOR, power fail, or
user reset
Interrupt, rising wakeup
Idle
Write to halt location
Figure 3-10. State Diagram
3.16 Resets
There are three asynchronous resets to the EP7211, these are NPOR, NPWRFL and NURESET. If
any of these is active, a system reset is generated internally. This will clear all internal registers in
the EP7211 to zero (except the DRAM refresh period register (DRFPR), and the RTC data and match
registers, which are only cleared by an active NPOR). This ensures that the DRAM contents and
system time is preserved through a user reset or power fail condition. Any reset will also reset the
CPU and cause it to start execution at the reset vector when the EP7211 returns to the Operating
State.
Internal to the EP7211, three different signals are used to reset storage elements. These are NPOR,
NSYSRES and NSTBY. NPOR is an external signal. NSTBY is equivalent to the external RUN
signal.
NPOR (Not Power On Reset) is the highest priority reset signal. When active (low), it will reset all
storage elements in the EP7211. NPOR active forces NSYSRES and NSTBY active. NPOR will
only be active after the EP7211 is first powered up and not during any other resets. NPOR active
will clear all flags in the status register apart from the cold reset flag (CLDFLG) bit, which is set.
NSYSRES (Not System Reset) is generated internally to the EP7211 if NPOR, NPWRFL or
NURESET are active. It is the second highest priority reset signal, used to asynchronously reset
most internal registers in the EP7211. NSYSRES active forces NSTBY and RUN low. NSYSRES
is used to reset the EP7211 and force it into the Standby State with no co-operation from software.
The CPU is also reset. The memory controller will place all DRAMs in self refresh mode, thus
DS352PP3
JUL 2001
71
Functional Description