DS925 Datasheet, PDF (99/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
GTY Transceiver Protocol Jitter Characteristics
For Table 124 through Table 129, the UltraScale Architecture GTY Transceiver User Guide (UG578) contains
recommended settings for optimal usage of protocol specific characteristics.
Table 124: Gigabit Ethernet Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
Min
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
–
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
Max
–
Units
UI
UI
Table 125: XAUI Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
3125
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
Min
–
Max
–
Units
UI
UI
Table 126: PCI Express Protocol Characteristics (GTY Transceivers)⁽¹⁾
Standard
Description
Condition
Line Rate (Mb/s)
PCI Express Transmitter Jitter Generation
PCI Express Gen 1 Total transmitter jitter
2500
PCI Express Gen 2 Total transmitter jitter
5000
PCI Express Gen 3^{(2) Total transmitter jitter uncorrelated}
Deterministic transmitter jitter uncorrelated
8000
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1 Total receiver jitter tolerance
2500
PCI Express Gen 2^{(2) Receiver inherent timing error}
Receiver inherent deterministic timing error
5000
PCI Express Gen 3⁽²⁾
Receiver sinusoidal
jitter tolerance
0.03 MHz–1.0 MHz
1.0 MHz–10 MHz
10 MHz–100 MHz
8000
Min
–
–
–
–
Note 3
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
Max Units
UI
UI
ps
ps
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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