DS925 Datasheet, PDF (48/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 62: PS-GTR Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Min
Typ
Max
PCI Express
–
100
–
SATA
25
125
150
F_GCLK
Reference clock frequency range. USB 3.0
DisplayPort
24 40/48/50/52 100
27
54
108
SGMII
–
125
–
T_RCLK
Reference clock rise time.
20% – 80%
–
200
T_FCLK
Reference clock fall time.
80% – 20%
–
200
Transceiver PLL only.
40
–
T_DCREF
Reference clock duty cycle.
USB 3.0 with reference
clock <40 MHz.
47.5
–
–
–
60
52.5
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
%
%
Table 63: PS-GTR Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
F_GTRTX
Serial data rate range.
1.25
–
T_RTX
TX rise time.
20%–80%
0.2
–
T_FTX
TX fall time.
80%–20%
0.2
–
V_TXOOBVDPP
Electrical idle amplitude.
–
–
T_{TXOOBTRANSITION} Electrical idle transition time.
–
–
T_J6.0
D_J6.0
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
6 Gb/s
–
–
T_J5.4
D_J5.4
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
5.4 Gb/s
–
–
T_J5.0
D_J5.0
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
5 Gb/s
–
–
T_J3.0
D_J3.0
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
3 Gb/s
–
–
T_J2.7
D_J2.7
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
2.7 Gb/s
–
–
T_J2.5
D_J2.5
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
2.5 Gb/s
–
–
T_J1.62
D_J1.62
Total jitter⁽¹⁾
–
Deterministic jitter⁽¹⁾
1.62 Gb/s
–
–
–
T_J1.5
D_J1.5
Total jitter⁽¹⁾
–
–
Deterministic jitter⁽¹⁾
1.5 Gb/s
–
–
T_J1.25
D_J1.25
Total jitter⁽¹⁾
–
Deterministic jitter⁽¹⁾
1.25 Gb/s
–
–
–
Notes:
1. All jitter values are based on a bit-error ratio of 10^-12.
Max
6.0
0.41
0.41
20
8
Units
Gb/s
UI
UI
mV
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
DS925 (v1.1) June 20, 2016
Advance Product Specification
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