DS925 Datasheet, PDF (74/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 91: Global Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^(1)(2)(3)
T_{PSMMCMCC_ZU2EG}
T_{PHMMCMCC_ZU2EG}
Global clock input and
input flip-flop (or latch)
with MMCM.
Setup
XCZU2EG
Hold
1.71
0.33
1.98
0.33
2.16
0.33
2.16
0.45
2.16
0.45
ns
ns
T_{PSMMCMCC_ZU3EG}
T_{PHMMCMCC_ZU3EG}
Setup
1.71 1.98 2.16 2.16 2.16
ns
XCZU3EG
Hold
0.33 0.33 0.33 0.45 0.45
ns
T_{PSMMCMCC_ZU4EV}
Setup
XCZU4EV
ns
T_{PHMMCMCC_ZU4EV}
Hold
ns
T_{PSMMCMCC_ZU5EV}
Setup
XCZU5EV
ns
T_{PHMMCMCC_ZU5EV}
Hold
ns
T_{PSMMCMCC_ZU6EG}
T_{PHMMCMCC_ZU6EG}
Setup
1.88 2.04 2.19 2.19 2.19
ns
XCZU6EG
Hold
0.42 0.42 0.42 0.71 0.71
ns
T_{PSMMCMCC_ZU7EV}
Setup
XCZU7EV
ns
T_{PHMMCMCC_ZU7EV}
Hold
ns
T_{PSMMCMCC_ZU9EG}
T_{PHMMCMCC_ZU9EG}
Setup
1.88 2.04 2.19 2.19 2.19
ns
XCZU9EG
Hold
0.42 0.42 0.42 0.71 0.71
ns
T_{PSMMCMCC_ZU11EG}
Setup
XCZU11EG
ns
T_{PHMMCMCC_ZU11EG}
Hold
ns
T_{PSMMCMCC_ZU15EG}
T_{PHMMCMCC_ZU15EG}
Setup
1.88 2.08 2.26 2.29 2.29
ns
XCZU15EG
Hold
0.36 0.36 0.36 0.50 0.64
ns
T_{PSMMCMCC_ZU17EG}
Setup
XCZU17EG
ns
T_{PHMMCMCC_ZU17EG}
Hold
ns
T_{PSMMCMCC_ZU19EG}
Setup
XCZU19EG
ns
T_{PHMMCMCC_ZU19EG}
Hold
ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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