DS925 Datasheet, PDF (38/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS Gigabit Ethernet Controller Interface
Table 46: RGMII Interface⁽¹⁾
Symbol
Description
Min
Max
Units
T_DCGEMTXCLK
T_GEMTXCKO
T_GEMRXDCK
T_GEMRXCKD
T_MDIOCLK
T_MDIOCKL
T_MDIOCKH
T_MDIODCK
T_MDIOCKD
T_MDIOCKO
F_GETXCLK
F_GERXCLK
F_{ENET_REF_CLK}
F_{TSU_REF_CLK}
Transmit clock duty cycle.
TXD output clock to out time.
RXD input setup time.
RXD input hold time.
MDC output clock period.
MDC low time.
MDC high time.
MDIO input data setup time.
MDIO input data hold time.
MDIO output data delay time.
RGMII_TX_CLK transmit clock frequency.
RGMII_RX_CLK receive clock frequency.
Ethernet reference clock frequency.
Time stamp unit reference clock frequency.
45
–0.5
0.8
0.8
400
160
160
80
0.0
–1.0
–
–
–
–
55
%
0.5
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
15
ns
125
MHz
125
MHz
125
MHz
250
MHz
Notes:
1. The test conditions are configured to the LVCMOS 2.5V I/O standard with a 12 mA drive strength, fast slew rate, and a 15
pF load.
X-Ref Target - Figure 7
RGMII_TX_CLK
RGMII_TX_D[3:0]
RGMII_TX_CTL
T_GEMTXCKO
RGMII_RX_CLK
RGMII_RX_D[3:0]
RGMII_RX_CTL
T_GEMRXDCK
MDIO_CLK
MDIO_IO (Input)
T_MDIODCK
MDIO_IO (Output)
T_GEMRXCKD
T_MDIOCKH
T_MDIOCKD
T_MDIOCKO
T_MDIOCLK
Figure 7: RGMII Interface Timing
T_MDIOCKL
ds925_RGMII_052915
DS925 (v1.1) June 20, 2016
Advance Product Specification
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