DS925 Datasheet, PDF (68/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
DSP48 Slice Switching Characteristics
Table 83: DSP48 Slice Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Maximum Frequency
F_MAX
F_{MAX_PATDET}
F_{MAX_MULT_NOMREG}
With all registers used.
891
775
645
644
600
With pattern detector.
794
687
571
562
524
Two register multiply without
MREG.
635
544
456
440
413
F_{MAX_MULT_NOMREG_PATDET}
Two register multiply without
MREG with pattern detect.
577
492
410
395
371
F_{MAX_PREADD_NOADREG}
F_{MAX_NOPIPELINEREG}
Without ADREG.
Without pipeline registers
(MREG, ADREG).
655
565
468
453
423
483
410
338
323
304
Without pipeline registers
F_{MAX_NOPIPELINEREG_PATDET} (MREG, ADREG) with pattern
detect.
448
379
314
299
280
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clock Buffers and Networks
Table 84: Clock Buffers Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Global Clock Switching Characteristics (Including BUFGCTRL)
F_MAX
Maximum frequency of a global clock tree
(BUFG).
891
775
667
725
667
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)
F_MAX
Maximum frequency of a global clock buffer with
input divide capability (BUFGCE_DIV).
891
775
667
725
667
Global Clock Buffer with Clock Enable (BUFGCE)
F_MAX
Maximum frequency of a global clock buffer with
clock enable (BUFGCE).
891
775
667
725
667
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)
F_MAX
Maximum frequency of a leaf clock buffer with
clock enable (BUFCE_LEAF).
891
775
667
725
667
GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
Maximum frequency of a serial transceiver clock
F_MAX
buffer with clock enable and clock input divide
512
512
512
512
512
capability.
Units
MHz
MHz
MHz
MHz
MHz
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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