DS925 Datasheet, PDF (29/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 41: ONFI (SDR Mode 0) Switching Characteristics⁽¹⁾ (Cont’d)
Symbol
Description
Min
Max
Units
T_ONFIRHW0
T_ONFIRP0
T_ONFIWC0
T_ONFIWH0
T_ONFIWP0
T_ONFIWB0
T_ONFIWHR0
RE_n High to WE_n Low
RE_n pulse width
WE_n cycle time
WE_n High hold time
WE_n pulse width
WE_n to Ready_n Low time
Command, address, or data input cycle to data output cycle
272.3
–
ns
60.0
–
ns
120.0
–
ns
60.0
–
ns
60.0
–
ns
–
100
ns
178.6
–
ns
Notes:
1. The test conditions are configured to the LVCMOS 1.8V I/O standard with an 8 mA drive strength, fast slew rate, and a
15 pF load.
X-Ref Target - Figure 1
WE_n
CLE
CE_n
ALE
IO[7:0]
T_ONFIWP#
T_ONFICLS#
T_ONFICLH#
T_ONFICS#
T_ONFICH#
T_ONFIALS#
T_ONFIALH#
T_ONFIDS#
Command
T_ONFIDH#
R/B_n
X-Ref Target - Figure 2
WE_n
CLE
CE_n
ALE
IO[7:0]
T_ONFIWB
ds925_onfi_sdr_command_092515
Figure 1: ONFI SDR Command Latch Timing
T_ONFIWP#
T_ONFIWH#
T_ONFICLS#
T_ONFICS#
T_ONFIALS#
T_ONFIALH#
T_ONFIDS#
Address
T_ONFIDH#
Figure 2: ONFI SDR Address Latch Timing
ds925_onfi_sdr_address_092115
DS925 (v1.1) June 20, 2016
Advance Product Specification
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