DS925 Datasheet, PDF (41/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS eMMC Standard Interface
Table 48: eMMC Standard Interface⁽¹⁾
Symbol
Description
Min
Max
Units
eMMC Standard Interface
T_DCEMMCHSCLK
eMMC clock duty cycle.
T_EMMCHSCKO
Clock to output delay, all outputs.
T_EMMCHSDCK
Input setup time, all inputs.
T_EMMCHSCKD
Input hold time, all inputs.
F_EMMCHSCLK
eMMC clock frequency.
eMMC High-Speed SDR Interface
45
–2.0
2.0
2.0
–
55
%
4.5
ns
–
ns
–
ns
25
MHz
T_DCEMMCHSCLK
eMMC high-speed SDR clock duty cycle.
T_EMMCHSCKO
Clock to output delay, all outputs.
T_EMMCHSDCK
Input setup time, all inputs.
T_EMMCHSCKD
Input hold time, all inputs.
F_EMMCHSCLK
eMMC high speed SDR clock frequency.
eMMC High-Speed DDR Interface
45
55
%
3.2
16.8
ns
4.7
–
ns
2.5
–
ns
–
50
MHz
T_DCEMMCDDRCLK eMMC high-speed DDR clock duty cycle.
T_EMMCDDRSCKO1 Data clock to output delay.
T_EMMCDDRDCK1
Data input setup time.
T_EMMCDDRCKD1
Data input hold time.
T_EMMCDDRSCKO2 Command clock to output delay.
T_EMMCDDRDCK2
Command input setup time.
T_EMMCDDRCKD2
Command input hold time.
F_EMMCDDRCLK
eMMC high-speed DDR clock frequency.
eMMC HS200 Interface
45
55
%
2.7
7.3
ns
1.4
–
ns
1.5
–
ns
3.2
16
ns
3.9
–
ns
2.5
–
ns
–
50
MHz
T_{DCEMMCHS200CLK}
T_EMMCHS200CKO
T_EMMCHS200DCK
T_EMMCHS200CKD
F_EMMCHS200CLK
eMMC HS200 clock duty cycle.
Clock to output delay, all outputs.
Input setup time, all inputs.
Input hold time, all inputs.
eMMC HS200 clock frequency.
45
55
%
1.0
3.4
ns
0.4
–
ns
0.4
–
ns
–
200
MHz
Notes:
1. The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load. For eMMC
high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other eMMC modes,
the test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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