DS925 Datasheet, PDF (20/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
LVDS DC Specifications (LVDS_25)
The LVDS_25 standard is available in the HD I/O banks. See the UltraScale Architecture SelectIO Resources
User Guide (UG571) for more information.
Table 22: LVDS_25 DC Specifications
Symbol
DC Parameter
Min Typ Max Units
V_CCO(1)
V_IDIFF
Supply voltage.
Differential input voltage:
(Q – Q), Q = High
(Q – Q), Q = High
2.375 2.500 2.625 V
100 350 600⁽²⁾ mV
V_ICM
Input common-mode voltage.
0.300 1.200 1.500 V
Notes:
1.
HD I/O banks only support LVDS_25 inputs. LVDS_25 inputs without internal termination
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the
Recommended
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2.
Maximum
when the
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LVDS DC Specifications (LVDS)
The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User
Guide (UG571) for more information.
Table 23: LVDS DC Specifications
Symbol
DC Parameter
Conditions
Min Typ Max Units
V_CCO(1)
V_ODIFF(2)
V_OCM(2)
V_IDIFF(3)
Supply voltage.
Differential output voltage:
(Q – Q), Q = High
(Q – Q), Q = High
Output common-mode voltage.
Differential input voltage:
(Q – Q), Q = High
(Q – Q), Q = High
1.710 1.800 1.890 V
R_T = 100Ω across Q and Q signals 247 350 600
mV
R_T = 100 Ω across Q and Q signals 1.000 1.250 1.425
V
100 350 600⁽³⁾ mV
V_{ICM_DC(4)}
V_{ICM_AC(5)}
Input common-mode voltage (DC coupling).
Input common-mode voltage (AC coupling).
0.300 1.200 1.425 V
0.600 – 1.100 V
Notes:
1.
In HP I/O banks, when LVDS is used
different from the specified level only
to ensure the input pin voltage levels
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V_IN I/O pin voltage.
2. V_OCM and V_ODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
3.
Maximum
when the
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only
4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0,
EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
DS925 (v1.1) June 20, 2016
Advance Product Specification
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