DS925 Datasheet, PDF (26/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS Switching Characteristics
PS Clocks
Table 33: PS Reference Clock Requirements⁽¹⁾
Symbol
Description
Min
T_JTPSCLK
PS_CLK RMS clock jitter tolerance.
–
T_DCPSCLK
PS_CLK duty cycle.
T_RFPSCLK
PS_CLK rise and fall time.
–
F_PSCLK
PS_CLK frequency.
27
Notes:
1. The values in this table are applicable to alternative PS reference clock inputs.
Typ
–
–
–
–
Max
60
Units
%
%
ns
MHz
Table 34: PS Crystal Requirements⁽¹⁾
Symbol
Description
Min
Typ
F_XTAL
T_FTXTAL
C_XTAL
R_ESR
C_SHUNT
Parallel resonance crystal frequency.
–
Frequency tolerance.
–20
Load capacitance for crystal parallel resonance.
–
Crystal ESR (16.8 and 19.2 MHz).
–
Crystal shunt capacitance.
–
32.8
–
12.5
70
1.4
Notes:
1. Required board components: Feedback resistor = 4.7 MΩ, PCB and pad capacitance = 1.5 pF,
C₁ and C₂ capacitance = 21 pF.
Table 35: PS PLL Switching Characteristics
Symbol
Description
F_LOCKPSPLL
F_PSPLLMAX
F_PSPLLMIN
F_PSPLLVCOMAX
F_PSPLLVCOMIN
PLL maximum lock time.
PLL maximum output frequency.
PLL minimum output frequency.
PLL maximum VCO frequency.
PLL minimum VCO frequency.
-3
100
1600
750
3000
1500
Speed Grade
-2
100
1600
750
3000
1500
Max
–
20
–
–
–
Units
KHz
ppm
pF
KΩ
pF
-1
100
1600
750
3000
1500
Units
µs
MHz
MHz
MHz
MHz
Table 36: PS Reset Assertion Timing Requirements
Symbol
Description
Min
Typ
Max
Units
T_PSPOR
T_PSRST
Required PS_POR_B assertion time.⁽¹⁾
10
–
Required PS_SRST_B assertion time.
–
–
µs
–
PS_CLK Clock Cycles
Notes:
1. The time PS_POR_B must be asserted Low after all the PS supply voltages reach minimum levels.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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