DS925 Datasheet, PDF (40/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 47: SD/SDIO Interface⁽¹⁾ (Cont’d)
Symbol
Description
Min
Max
Units
F_SDIDCLK
F_SDSCLK
Clock frequency in identification mode.
Standard SD device clock frequency.
–
400
KHz
–
19
MHz
Notes:
1. The test conditions are configured for all SD/SDIO modes except SD/SDIO standard mode with a 12 mA drive strength and
a 30 pF load. For SD/SDIO standard mode, the test conditions use a 8 mA drive strength and a 30 pF load.
X-Ref Target - Figure 8
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
T_SDHSDCK
T_SDHSCKD
T_SDHSCKO
Figure 8: SD/SDIO Interface High Speed Mode Timing Diagram
DS925_SD_SDIO_HS_100915
X-Ref Target - Figure 9
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
T_SDSDCK
T_SDSCKO
T_SDSCKD
Figure 9: SD/SDIO Interface Standard Mode Timing Diagram
DS925_SD_SDIO_SM_100915
DS925 (v1.1) June 20, 2016
Advance Product Specification
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