DS925 Datasheet, PDF (43/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS SPI Controller Interface
Table 50: SPI Interfaces⁽¹⁾
Symbol
Description
Min
Max
Units
SPI Master Interface
T_DCMSPICLK
SPI master mode clock duty cycle.
T_MSPISSSCLK
Slave select asserted to first active clock edge.
T_MSPISCLKSS
Last active clock edge to slave select deasserted.
T_MSPIDCK
Input setup time for MISO.
T_MSPICKD
Input hold time for MISO.
T_MSPICKO
MOSI and slave select clock to out delay.
F_MSPICLK
SPI master device clock frequency.
F_{SPI_REF_CLK}
SPI reference clock frequency.
SPI Slave Interface
45
1⁽²⁾
1⁽²⁾
–1.0
5.0⁽³⁾
–2.0
–
–
55
–
–
–
–
5.0
50
200
%
F_{SPI_REFCLK} cycles
F_{SPI_REFCLK} cycles
ns
ns
ns
MHz
MHz
T_SSPIDCK
Slave select asserted to first active clock edge.
5
T_SSPICKD
Last active clock edge to slave select deasserted.
5
T_SSPICKO
Input setup time for MOSI and slave select.
5.0
T_SSPISSCLK
Input hold time for MOSI and slave select.
5.0
T_SSPICLKSS
MISO clock to out delay.
0.0
F_SSPICLK
SPI slave mode device clock frequency.
–
F_{SPI_REF_CLK}
SPI reference clock frequency.
–
–
–
–
–
13.0
25
200
F_{SPI_REFCLK} cycles
F_{SPI_REFCLK} cycles
ns
ns
ns
MHz
MHz
Notes:
1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a
30 pF load.
2.
Valid when two SPI_REF_CLK delays are programmed
T_MSPISCLKSS in the SPI delay_reg0 register.
between
CS
and
CLK
for
T_MSPISSSCLK,
and
between
CLK
and
CS
for
3. The T_MSPICKD Min = (1/F_{SPI_REF_CLK}) for frequencies below 50 MHz.
X-Ref Target - Figure 12
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
T_MSPISSCLK
Dn
Dn–1
T_MSPICKD
T_MSPICKO
Dn–2
T_MSPICLKSS
Dn–3
D0
SPI{0,1}_MISO
T_MSPIDCK
Dn
Dn–1
Dn–2
Figure 12: SPI Master (CPHA = 0) Interface Timing
ds925_SPIM_0_052915
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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