DS925 Datasheet, PDF (67/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
UltraRAM Switching Characteristics
The UltraScale Architecture and Product Overview (DS890) lists the Zynq UltraScale+ MPSoC that include
this memory.
Table 81: UltraRAM Switching Characteristics
Symbol
Description
Maximum Frequency
F_MAX
UltraRAM maximum frequency with
OREG_B.
F_{MAX_ECC}
UltraRAM maximum frequency without
OREG_B and EN_ECC_RD_B = True.
UltraRAM maximum frequency with
F_{MAX_NORPIPELINE} OREG_B = False and
EN_ECC_RD_B = False.
T_PW(1)
T_RSTPW
Minimum pulse width.
Asynchronous reset minimum pulse
width.
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Units
650
600
600
500
500
MHz
450
400
400
325
325
MHz
550
500
500
425
425
MHz
650
700
700
800
800
ps
550
600
600
650
650
ps
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher
frequencies.
Input/Output Delay Switching Characteristics
Table 82: Input/Output Delay Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
F_REFCLK
REFCLK frequency
(component mode).
REFCLK frequency (native mode).
200 to
2400
200 to 800
200 to
2400
200 to
2133
T_{MINPER_RST}
T_{IDELAY_RESOLUTION}/
T_{ODELAY_RESOLUTION}
Minimum reset pulse width.
IDELAY/ODELAY chain resolution.
52.00
2.5 to 15
Units
MHz
MHz
ns
ps
DS925 (v1.1) June 20, 2016
Advance Product Specification
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