DS925 Datasheet, PDF (31/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 42: ONFI NV-DDR (Mode 5) Switching Characteristics
Symbol
Description
Min
Max
Units
T_ONFIDDRCK5
T_ONFIDDRCKL5
T_ONFIDDRCKH5
T_ONFIDDRCALS5
T_ONFIDDRCALH5
T_ONFIDDRCS5
T_ONFIDDRCH5
T_ONFIDDRCAD5
T_ONFIDDRDQSS5
T_ONFIDDRWPRE5
T_ONFIDDRDSS5
T_ONFIDDRDSH5
T_ONFIDDRDQSH5
T_ONFIDDRDQSL5
T_ONFIDDRDS5
T_ONFIDDRDH5
T_ONFIDDRWPST5
T_ONFIDDRDSC5
T_{ONFIDDRDQSCK5}
T_ONFIDDRCLK5
Clock cycle time
Clock cycle Low time
Clock cycle High time
W/R_n, CLE, and ALE setup time
W/R_n, CLE and ALE hold time
CE_n setup time
CE_n hold time
Command, address, data delay time
Data input to first DQS latching transition
DQS write preamble
DQS falling edge to CLK rising setup time
DQS falling edge to CLK rising hold time
DQS input High pulse width
DQS input Low pulse width
Data setup time
Data hold time
DQS write post-amble
Average DQS cycle time
Access window of DQS from CLK
NAND clock frequency
10
0.43
0.43
2.20
2.20
15.00
20.00
25
0.75
1.5
0.2
0.2
0.4
0.4
0.9
0.9
1.5
10
3
-
–
0.57
0.57
–
–
–
–
–
1.25
–
–
–
0.6
0.6
–
–
–
–
25
100
ns
T_ONFIDDRCK5
T_ONFIDDRCK5
ns
ns
ns
ns
ns
T_ONFIDDRCK5
T_ONFIDDRCK5
T_ONFIDDRCK5
T_ONFIDDRCK5
T_ONFIDDRCK5
T_ONFIDDRCK5
ns
ns
T_ONFIDDRCK5
ns
ns
MHz
Notes:
1. The test conditions are configured to the LVCMOS 1.8V and LVCMOS 3.3V I/O standards with a 12 mA drive strength, fast
slew rate, and a 30 pF load.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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