DS925 Datasheet, PDF (79/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
GTH Transceiver Switching Characteristics
Consult the UltraScale Architecture GTH Transceiver User Guide (UG576) for further information.
Table 97: GTH Transceiver Performance
Symbol
Description
Output
Divider
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Units
F_GTHMAX
F_GTHMIN
GTH maximum line rate.
GTH minimum line rate.
16.375⁽¹⁾
0.5
Min Max
16.375⁽¹⁾
0.5
Min Max
12.5
0.5
Min Max
12.5
0.5
Min Max
10.3125
0.5
Min Max
Gb/s
Gb/s
1
4
12.5
4
12.5
4
8.5
4
8.5
4
8.5 Gb/s
2
F_GTHCRANGE
CPLL line rate
range⁽²⁾.
4
8
2
6.25
2
6.25
2
4.25
2
4.25
2
4.25 Gb/s
1 3.125 1 3.125 1 2.125 1 2.125 1 2.125 Gb/s
0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.0625 0.5 1.0625 Gb/s
16
N/A
Gb/s
Min Max Min Max Min Max Min Max Min Max
1
9.8 16.375 9.8 16.375 9.8 12.5 9.8 12.5 9.8 10.3125 Gb/s
2
4.9 8.1875 4.9 8.1875 4.9 8.15 4.9 8.1875 4.9 8.15 Gb/s
F_GTHQRANGE1
QPLL0 line
rate range⁽³⁾.
4
2.45 4.09375 2.45 4.09375 2.45 4.075 2.45 4.09375 2.45 4.075 Gb/s
8
1.225 2.04688 1.225 2.04688 1.225 2.0375 1.225 2.04688 1.225 2.0375 Gb/s
16
0.6125 1.02344 0.6125 1.02344 0.6125 1.01875 0.6125 1.02344 0.6125 1.01875 Gb/s
Min Max Min Max Min Max Min Max Min Max
1
8.0 13.0 8.0 13.0 8.0 12.5 8.0 12.5 8.0 10.3125 Gb/s
2
F_GTHQRANGE2
QPLL1 line
rate range⁽⁴⁾.
4
8
4.0
6.5
4.0
6.5
4.0
6.5
4.0
6.5
4.0
6.5 Gb/s
2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 Gb/s
1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 Gb/s
16
0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
Min Max Min Max Min Max Min Max Min Max
F_CPLLRANGE CPLL frequency range.
2
6.25
2
6.25
2
4.25
2
4.25
2
4.25 GHz
F_QPLL0RANGE QPLL0 frequency range. 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 GHz
F_QPLL1RANGE QPLL1 frequency range. 8
13
8
13
8
13
8
13
8
13 GHz
Notes:
1. GTH transceiver line rates in the SFVC784 package support data rates up to 12.5 Gb/s.
2. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.
4. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.
Table 98: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
Description
All Speed Grades
Units
F_GTHDRPCLK GTHDRPCLK maximum frequency.
MHz
DS925 (v1.1) June 20, 2016
Advance Product Specification
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