DS925 Datasheet, PDF (27/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 37: PS Clocks Switching Characteristics
Symbol
Description
F_{TOPSW_MAINMAX}
F_{TOPSW_LSBUSMAX}
F_GDMAMAX
F_DPDMAMAX
F_{LPD_SWITCH_CTRLMAX}
TOPSW_MAIN maximum frequency.
TOPSW_LSBUS maximum frequency.
GDMA maximum frequency.
DPDMA maximum frequency.
LPD_SWITCH_CTRL maximum
frequency.
F_{LPD_LSBUS_CTRLMAX}
LPD_LSBUS_CTRL maximum
frequency.
F_ADMAMAX
F_{APLL_TO_LPDMAX}
F_{DPLL_TO_LPDMAX}
F_{VPLL_TO_LPDMAX}
F_{IOPLL_TO_LPDMAX}
F_{RPLL_TO_FPDMAX}
ADMA maximum frequency.
APLL_TO_LPD maximum frequency.
DPLL_TO_LPD maximum frequency.
VPLL_TO_LPD maximum frequency.
IOPLL_TO_LPD maximum frequency.
RPLL_TO_FPD maximum frequency.
Speed Grade
Units
-3
-2
-1
600
533
MHz
100
100
MHz
600
600
MHz
600
600
MHz
600
500
MHz
100
100
MHz
600
500
MHz
533
533
MHz
533
533
MHz
533
533
MHz
533
533
MHz
533
533
MHz
PS Configuration
Table 38: Processor Configuration Access Port Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
F_PCAPCK
Maximum processor configuration access port
(PCAP) frequency.
200
200
200
166
166
Units
MHz
Table 39: Boundary-Scan Port Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
F_TCK
T_TAPTCK/T_TCKTAP
T_TCKTDO
JTAG clock maximum frequency.
TMS and TDI setup and hold.
TCK falling edge to TDO output.
25
4.0/2.0
16.1
25
4.0/2.0
16.1
25
4.0/2.0
16.1
15
5.0/2.0
24
15
MHz
5.0/2.0 ns, Min
24 ns, Max
Notes:
1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
27