DS925 Datasheet, PDF (102/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Integrated Interface Block for Interlaken
More information and documentation on solutions using the integrated interface block for Interlaken can
be found at UltraScale Interlaken. The UltraScale Architecture and Product Overview (DS890) lists how
many blocks are in each Zynq UltraScale+ MPSoCs.
Table 130: Maximum Performance for Interlaken Designs
Symbol
Description
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
F_{RX_SERDES_CLK}
Receive serializer/
deserializer clock
440.79
440.79
195.32
195.32
161.14
MHz
Transmit
F_{TX_SERDES_CLK} serializer/
deserializer clock
440.79
440.79
195.32
195.32
161.14
MHz
F_{DRP_CLK}
Dynamic
reconfiguration
port clock
250.00
250.00
250.00
250.00
250.00
MHz
Min Max Min Max Min Max Min Max Min Max
F_{CORE_CLK}
Interlaken core
clock
300.00⁽¹⁾
460.00⁽²⁾
300.00⁽¹⁾
460.00⁽²⁾
300.00⁽¹⁾
MHz
300.00 322.27
429.69 300.00 322.27
412.50⁽²⁾
MHz
F_{LBUS_CLK}
Interlaken local
bus clock
300.00 349.52 300.00 349.52 300.00 322.27
300.00 322.27 MHz
Notes:
1. The minimum value for CORE_CLK is 300 MHz for the 12 x 12.5G Interlaken configuration.
2. The minimum value for CORE_CLK is 412.5 MHz for the 6 x 25.78125G Interlaken configuration. This 6 x 25.78125G
configuration is not supported in the lane logic-only mode.
Integrated Interface Block for 100G Ethernet MAC and PCS
More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be
found at UltraScale Integrated 100G Ethernet MAC/PCS. The UltraScale Architecture and Product Overview
(DS890) lists how many blocks are in each Zynq UltraScale+ MPSoCs.
Table 131: Maximum Performance for 100G Ethernet Designs
Symbol
Description
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2⁽¹⁾
-1
-2
-1
Units
F_{TX_CLK}
F_{RX_CLK}
F_{RX_SERDES_CLK}
F_{DRP_CLK}
Transmit clock
Receive clock
Receive serializer/deserializer clock
Dynamic reconfiguration port clock
390.625
390.625
390.625
250.00
390.625
390.625
390.625
250.00
322.223
322.223
322.223
250.00
322.223
322.223
322.223
250.00
322.223
322.223
322.223
250.00
MHz
MHz
MHz
MHz
Notes:
1. The maximum clock frequency of 390.625 MHz only applies to the CAUI-10 interface. The maximum clock frequency for
the CAUI-4 interface is 322.223 MHz.
DS925 (v1.1) June 20, 2016
Advance Product Specification
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