DS925 Datasheet, PDF (71/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
The pin-to-pin numbers in Table 87 through Table 89 are based on the clock root placement in the center
of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 87: Global Clock Input to Output Delay Without MMCM (Near Clock Region)
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM.
T_ICKOF
Global clock input and output
XCZU2EG
4.40
4.82
5.22
5.67
5.97
ns
flip-flop without MMCM (near clock
region).
XCZU3EG
4.40
4.82
5.22
5.67
5.97
ns
XCZU4EV
ns
XCZU5EV
ns
XCZU6EG
5.42
5.76
6.16
7.10
7.16
ns
XCZU7EV
ns
XCZU9EG
5.42
5.76
6.16
7.10
7.16
ns
XCZU11EG
ns
XCZU15EG 5.49
6.05
6.57
7.28
7.82
ns
XCZU17EG
ns
XCZU19EG
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
DS925 (v1.1) June 20, 2016
Advance Product Specification
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