DS925 Datasheet, PDF (97/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 122: GTY Transceiver Receiver Switching Characteristics
Symbol
Description
Condition
F_GTYRX
T_RXELECIDLE
Serial data rate
Time for RXELECIDLE to respond to loss or restoration of
data
R_XOOBVDPP
R_XSST
OOB detect threshold peak-to-peak
Receiver spread-spectrum tracking⁽¹⁾ Modulated at 33 kHz
R_XRL
Run length (CID)
Bit rates ≤ 6.6 Gb/s
R_XPPMTOL
Data/REFCLK PPM offset tolerance
Bit rates > 6.6 Gb/s
and ≤ 8.0 Gb/s
Bit rates > 8.0 Gb/s
SJ Jitter Tolerance⁽²⁾
J_{T_SJ32.75}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ16.375}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ12.5}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ11.3}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ10.32_QPLL} Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ10.32_CPLL} Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ9.8}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ8.0_QPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ8.0_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ6.6_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ5.0}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ4.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.75}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.2}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.2L}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ2.5}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ1.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ500}
Sinusoidal jitter (CPLL)⁽³⁾
SJ Jitter Tolerance with Stressed Eye⁽²⁾
32.75 Gb/s
16.375 Gb/s
12.5 Gb/s
11.3 Gb/s
10.32 Gb/s
10.32 Gb/s
9.8 Gb/s
8.0 Gb/s
8.0 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s⁽⁴⁾
3.2 Gb/s⁽⁵⁾
2.5 Gb/s⁽⁶⁾
1.25 Gb/s⁽⁷⁾
500 Mb/s
J_{T_TJSE3.2}
J_{T_TJSE6.6}
J_{T_SJSE3.2}
J_{T_SJSE6.6}
Total jitter with stressed eye⁽⁸⁾
Sinusoidal jitter with stressed eye⁽⁸⁾
3.2 Gb/s
6.6 Gb/s
3.2 Gb/s
6.6 Gb/s
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10^–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter with RX equalizer enabled. DFE disabled.
Min
0.500
–
–
Typ
–
–
–
–
–
–
–
Max Units
F_GTYMAX Gb/s
–
ns
mV
ppm
UI
ppm
ppm
ppm
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
–
–
UI
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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