DS925 Datasheet, PDF (34/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 43: Generic Quad-SPI Interface⁽¹⁾ (Cont’d)
Symbol
Description
Load
Conditions⁽²⁾
Min
Max
Units
T_QSPIDCK3
Setup time, all inputs.
15 pF
13.4
–
ns
30 pF
14.1
–
ns
T_QSPICKD3
Hold time, all inputs.
15 pF
0.0
–
ns
30 pF
0.0
–
ns
F_QSPIREFCLK3 Quad-SPI reference clock frequency.
15 pF
30 pF
–
160
–
160
MHz
MHz
F_QSPICLK3
Quad-SPI clock frequency.
15 pF
30 pF
–
40
–
40
MHz
MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O
standard.
T_DCQSPICLK4 Quad-SPI clock duty cycle.
15 pF
45
55
%
30 pF
45
55
%
T_QSPISSSCLK4 Slave select asserted to next clock edge.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPISCLKSS4 Clock edge to slave select deasserted.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPICKO4
Clock to output delay, all outputs.
15 pF
5.2 14.8
ns
30 pF
5.2 14.8
ns
T_QSPIDCK4
Setup time, all inputs.
15 pF
13.9
–
ns
30 pF
14.9
–
ns
T_QSPICKD4
Hold time, all inputs.
15 pF
0.0
–
ns
30 pF
0.0
–
ns
F_QSPIREFCLK4 Quad-SPI reference clock frequency.
15 pF
30 pF
–
160
–
160
MHz
MHz
F_QSPICLK4
Quad-SPI clock frequency.
15 pF
30 pF
–
40
–
40
MHz
MHz
Notes:
1. The test conditions are configured for the generic Quad-SPI interface at 150/100 MHz with a 12 mA drive strength and fast
slew rate. The test conditions are configured for the generic Quad-SPI interface at 40 MHz with an 8 mA drive strength and
fast slew rate.
2. 30 pF loads are for dual-parallel stacked or stacked modes.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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