DS925 Datasheet, PDF (73/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Input Parameter Guidelines
The pin-to-pin numbers in Table 90 and Table 91 are based on the clock root placement in the center of
the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 90: Global Clock Input Setup and Hold With 3.3V HD I/O without MMCM
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^(1)(2)(3)
T_{PSFD_ZU2EG}
T_{PHFD_ZU2EG}
T_{PSFD_ZU3EG}
T_{PHFD_ZU3EG}
T_{PSFD_ZU4EV}
T_{PHFD_ZU4EV}
T_{PSFD_ZU5EV}
T_{PHFD_ZU5EV}
T_{PSFD_ZU6EG}
T_{PHFD_ZU6EG}
T_{PSFD_ZU7EV}
T_{PHFD_ZU7EV}
T_{PSFD_ZU9EG}
T_{PHFD_ZU9EG}
T_{PSFD_ZU11EG}
T_{PHFD_ZU11EG}
T_{PSFD_ZU15EG}
T_{PHFD_ZU15EG}
T_{PSFD_ZU17EG}
T_{PHFD_ZU17EG}
T_{PSFD_ZU19EG}
T_{PHFD_ZU19EG}
Global clock input and Setup
–0.67 –0.67 –0.67 –0.80 –0.80 ns
input flip-flop (or latch)
without MMCM.
XCZU2EG
Hold
1.76
1.97
2.09
2.54
2.76
ns
Setup
–0.67 –0.67 –0.67 –0.80 –0.80 ns
XCZU3EG
Hold
1.76 1.97 2.09 2.54 2.76
ns
Setup
ns
XCZU4EV
Hold
ns
Setup
ns
XCZU5EV
Hold
ns
Setup
–1.06 –1.06 –1.06 –1.06 –1.06 ns
XCZU6EG
Hold
2.40 2.59 2.71 3.47 3.54
ns
Setup
ns
XCZU7EV
Hold
ns
Setup
–1.06 –1.06 –1.06 –1.06 –1.06 ns
XCZU9EG
Hold
2.40 2.59 2.71 3.47 3.54
ns
Setup
ns
XCZU11EG
Hold
ns
Setup
–1.07 –1.07 –1.07 –1.24 –1.24 ns
XCZU15EG
Hold
2.39 2.74 2.94 3.53 3.91
ns
Setup
ns
XCZU17EG
Hold
ns
Setup
ns
XCZU19EG
Hold
ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
73