DS925 Datasheet, PDF (91/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
GTY Transceiver Switching Characteristics
Consult www.xilinx.com/products/technology/high-speed-serial for further information.
Table 115: GTY Transceiver Performance
Symbol
Description
Output
Divider
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Units
F_GTYMAX
GTY maximum line
rate
32.75
28.21
12.5
28.21
12.5
Gb/s
F_GTYMIN
GTY minimum line rate
0.5
Min Max
0.5
Min Max
0.5
Min Max
0.5
Min Max
0.5
Min Max
Gb/s
1
4.0 12.5 4.0 12.5 4.0
8.5
4.0 12.5 4.0
8.5 Gb/s
2
2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 Gb/s
F_GTYCRANGE
CPLL line
rate range⁽¹⁾
4
8
1.0 3.125 1.0 3.125 1.0 2.125 1.0 3.125 1.0 2.125 Gb/s
0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.5625 0.5 1.0625 Gb/s
16
N/A
Gb/s
32
N/A
Gb/s
Min Max Min Max Min Max Min Max Min Max
1
19.6 32.75 19.6 28.21
N/A
19.6 28.21
N/A
Gb/s
1
9.8 16.375 9.8 16.375 9.8 12.5 9.8 16.375 9.8 12.5 Gb/s
F_GTYQRANGE1
QPLL0 line
rate range⁽²⁾
2
4
4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 Gb/s
2.45 4.09375 2.45 4.09375 2.45 4.09375 2.45 4.09375 2.45 4.09375 Gb/s
8
1.225 2.04688 1.225 2.04688 1.225 2.04688 1.225 2.04688 1.225 2.04688 Gb/s
16 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 Gb/s
Min Max Min Max Min Max Min Max Min Max
1
16.0 26.0 16.0 26.0
N/A
16.0 26.0
N/A
Gb/s
1
8.0 13.0 8.0 13.0 8.0 12.5 8.0 13.0 8.0 12.5 Gb/s
F_GTYQRANGE2
QPLL1 line
rate range⁽³⁾
2
4
4.0
6.5
4.0
6.5
4.0
6.5
4.0
6.5
4.0
6.5 Gb/s
2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 Gb/s
8
1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 Gb/s
16
0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
Min Max Min Max Min Max Min Max Min Max
F_CPLLRANGE
F_QPLL0RANGE
CPLL frequency range
QPLL0 frequency
range
2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 GHz
9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 GHz
F_QPLL1RANGE
QPLL1 frequency
range
8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 GHz
Notes:
1. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
2. The values listed are the rounded results of the calculated equation (2 x QPLL0_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (2 x QPLL1_Frequency)/Output_Divider.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
91