DS925 Datasheet, PDF (45/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS CAN Controller Interface
Table 51: CAN Interface⁽¹⁾
Symbol
Description
T_PWCANRX
T_PWCANTX
F_{CAN_REF_CLK}
Receive pulse width.
Transmit pulse width.
Internally sourced CAN reference clock frequency.
Externally sourced CAN reference clock frequency.
Min
1.0
1.0
–
–
Max
–
–
100
40
Units
µs
µs
MHz
MHz
Notes:
1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a
15 pF load.
PS DAP Interface
Table 52: DAP Interface⁽¹⁾
Symbol
Description⁽²⁾
Min
Max
Units
T_PDAPDCK
T_PDAPCKD
T_PDAPCKO
T_PDAPCLK
PS DAP input setup time.
PS DAP input hold time.
PS DAP clock to out delay.
PS DAP clock frequency.
3.0
–
2.0
–
–
10.86
–
44
ns
ns
ns
MHz
Notes:
1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a
15 pF load.
2. PS DAP interface signals connect to MIO pins.
X-Ref Target - Figure 16
DAP_TCK
DAP_TMS, DAP_TDI
DAP_TDO
T_PDAPDCK
T_PDAPCKD
T_PDAPCKO
Figure 16: Processor JTAG Interface Timing
ds925_JTAG_071915
PS UART Interface
Table 53: UART Interface⁽¹⁾
Symbol
Description
Min
Max
Units
BAUD_TXMAX
BAUD_RXMAX
F_UARTCLK
Transmit baud rate.
Receive baud rate.
UART clock frequency.
–
6.25⁽²⁾
Mb/s
–
6.25⁽²⁾
Mb/s
–
100
MHz
Notes:
1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a
15 pF load.
2. An additional reference clock (uart_clk) is needed.
DS925 (v1.1) June 20, 2016
Advance Product Specification
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