DS925 Datasheet, PDF (35/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 44: Linear Quad-SPI Interface⁽¹⁾
Symbol
Description
Load
Conditions⁽²⁾
Min
Max
Units
Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled. LVCMOS 1.8V or
LVCMOS 3.3V I/O standards.
T_DCQSPICLK5 Quad-SPI clock duty cycle.
15 pF
45
55
%
30 pF
45
55
%
T_QSPISSSCLK5 Slave select asserted to next clock edge.
15 pF
5.0
–
ns
30 pF
5.0
–
ns
T_QSPISCLKSS5 Clock edge to slave select deasserted.
15 pF
5.0
–
ns
30 pF
5.0
–
ns
T_QSPICKO5
Clock to output delay, all outputs.
15 pF
3.2
7.4
ns
30 pF
3.2
7.4
ns
T_QSPIDCK5
Setup time, all inputs.
15 pF
1.9
–
ns
30 pF
1.9
–
ns
T_QSPICKD5
Hold time, all inputs.
15 pF
0.0
–
ns
30 pF
0.0
–
ns
F_QSPIREFCLK5 Quad-SPI reference clock frequency.
15 pF
30 pF
–
200
–
200
MHz
MHz
F_QSPICLK5
Quad-SPI device clock frequency.
15 pF
30 pF
–
100
–
100
MHz
MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O
standard.
T_DCQSPICLK6 Quad-SPI clock duty cycle.
15 pF
45
55
%
30 pF
45
55
%
T_QSPISSSCLK6 Slave select asserted to next clock edge.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPISCLKSS6 Clock edge to slave select deasserted.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPICKO6
Clock to output delay, all outputs.
15 pF
5.2 14.8
ns
30 pF
5.2 14.8
ns
T_QSPIDCK6
Setup time, all inputs.
15 pF
13.4
–
ns
30 pF
13.4
–
ns
T_QSPICKD6
Hold time, all inputs.
15 pF
0.0
–
ns
30 pF
0.0
–
ns
F_QSPIREFCLK6 Quad-SPI reference clock frequency.
15 pF
30 pF
–
160
–
160
MHz
MHz
F_QSPICLK6
Quad-SPI device clock frequency.
15 pF
30 pF
–
40
–
40
MHz
MHz
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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