DS925 Datasheet, PDF (108/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
06/20/2016
11/24/2015
Version
1.1
1.0
Description of Revisions
Updated the Summary description. In Table 1, revised V_IN for HP I/O banks and added
clarifications to some descriptions and symbols. Added I_RPU, I_RPD, and Note 4 to Table 2
and updated V_{PS_MGTRAVCC}, the PL System Monitor section, and Note 3 and Note 5.
Updated Note 5 in Table 5. Updated the PS Power-On/Off Power Supply Sequencing
section including all the voltage supply names. Added MIPI_DPHY_DCI to Table 13,
Table 14, and Table 16. Updated Table 22, including removing the V_CCO specification and
adding Note 1. Added Note 1 to Table 23. Updated Table 24 speed specifications for
Vivado Design Suite 2016.1. Added values to Table 27. Updated the -2 value in Table 28.
Added F_DPLIVEVIDEO and updated F_FCIDMACLK in Table 32. Added VCO frequencies to
Table 35. Added the T_PSPOR minimum to Table 36 and updated Note 1. Added Table 37.
Added value delineation over V_CCINT operating voltages in Table 38. Revised values for
F_TCK and T_TAPTCK/T_TCKTAP in Table 39 and added value delineation over V_CCINT operating
voltages. Updated Note 1 in Table 40, Table 41, and Table 42. Revised some units and
Note 1 in Table 43 and Table 44. Removed Figure 6: Quad-SPI Interface (Feedback Clock
Disabled) Timing. Updated Note 1 of Table 45. Added F_{TSU_REF_CLK} to Table 46 and
updated Note 1. In Table 47, revised T_DCSDHSCLK1, T_DCSDHSCLK2, and T_DCSDHSCLK3 and
Note 1. In Table 48, revised Note 1. In Table 49, revised Note 1. Revised Table 50,
including Note 1, and added Note 2 and Note 3. In Table 51, Table 52, Table 53, and
Table 55, revised Note 1. Updated Table 72. Replaced Table 74. Updated Table 75 and
Table 76. Updated the tables in the I/O Standard Adjustment Measurement Methodology
section. In Table 80, added the Block RAM and FIFO Clock-to-Out Delays section. Updated
the R_IN and C_EXT values in Table 59 and Table 95. Updated the -2 (0.72V) and -1 (0.72V)
values and added Note 1 to Table 97. Added Table 100 and Table 118. Added Note 2 to
Table 112. Revised data in Table 115. Revised Table 120. Revised data and added notes
to Table 130 and Table 131. Moved Table 133. Revised INL in Table 134. Added notes to
Table 135 and Table 136. In Table 138, updated the I_PSFS description.
Initial Xilinx release.
DS925 (v1.1) June 20, 2016
Advance Product Specification
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