DS925 Datasheet, PDF (69/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
MMCM Switching Characteristics
Table 85: MMCM Specification
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
MMCM_F_INMAX
MMCM_F_INMIN
MMCM_F_INJITTER
Maximum input clock frequency.
Minimum input clock frequency.
Maximum input clock period jitter.
Input duty cycle range: 10–49 MHz.
1066
933
800
933
800 MHz
10
10
10
10
10
MHz
< 20% of clock input period or 1 ns Max
25–75
%
Input duty cycle range: 50–199 MHz.
30–70
%
MMCM_F_INDUTY
Input duty cycle range: 200–399 MHz.
35–65
%
Input duty cycle range: 400–499 MHz.
40–60
%
Input duty cycle range: >500 MHz.
45–55
%
MMCM_F_{MIN_PSCLK}
Minimum dynamic phase shift clock
frequency.
0.01
0.01
0.01
0.01
0.01 MHz
MMCM_F_{MAX_PSCLK}
Maximum dynamic phase shift clock
frequency.
550
500
450
500
450 MHz
MMCM_F_VCOMIN
MMCM_F_VCOMAX
MMCM_F_BANDWIDTH
Minimum MMCM VCO frequency.
Maximum MMCM VCO frequency.
Low MMCM bandwidth at typical.⁽¹⁾
High MMCM bandwidth at typical.⁽¹⁾
800
1600
1.00
4.00
800
1600
1.00
4.00
800
1600
1.00
4.00
800
1600
1.00
4.00
800
1600
1.00
4.00
MHz
MHz
MHz
MHz
MMCM_T_{STATPHAOFFSET}
Static phase offset of the MMCM
outputs.⁽²⁾
0.12
0.12
0.12
0.12
0.12
ns
MMCM_T_OUTJITTER
MMCM_T_OUTDUTY
MMCM output jitter.
MMCM output clock duty cycle
precision.⁽⁴⁾
Note 3
0.165 0.20
0.20
0.20
0.20
ns
MMCM_T_LOCKMAX
MMCM_F_OUTMAX
MMCM_F_OUTMIN
MMCM maximum lock time for
MMCM_F_PFDMIN.
MMCM maximum output frequency.
MMCM minimum output
frequency.⁽⁴⁾⁽⁵⁾
100
891
6.25
100
775
6.25
100
667
6.25
100
725
6.25
100
667
6.25
µs
MHz
MHz
MMCM_T_EXTFDVAR
MMCM_RST_MINPULSE
MMCM_F_PFDMAX
External clock feedback variation.
Minimum reset pulse width.
Maximum frequency at the phase
frequency detector.
< 20% of clock input period or 1 ns Max
5.00
5.00
5.00
5.00
5.00
ns
550
500
450
500
450 MHz
MMCM_F_PFDMIN
Minimum frequency at the phase
frequency detector.
10
10
10
10
10
MHz
MMCM_T_FBDELAY
Maximum delay in the feedback path.
5 ns Max or one clock cycle
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter
frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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