DS925 Datasheet, PDF (93/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 118: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask⁽¹⁾
Symbol
Description
Offset
Frequency
Min
Typ
Max
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–112
phase noise mask at
100 kHz
–
–
–128
REFCLK frequency = 156.25 MHz.
1 MHz
–
–
–145
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–103
QPLL_REFCLKMASK
phase noise mask at
REFCLK frequency = 312.5 MHz.
100 kHz
–
–
–123
1 MHz
–
–
–143
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–98
phase noise mask at
100 kHz
–
–
–117
REFCLK frequency =625 MHz.
1 MHz
–
–
–140
10 kHz
–
–
–112
CPLL reference clock select phase noise _{100 kHz}
–
–
–128
mask at REFCLK
frequency = 156.25 MHz.
1 MHz
–
–
–145
50 MHz
–
–
–145
10 kHz
–
–
–103
CPLL_REFCLKMASK
CPLL reference clock select phase noise ^{100 kHz}
mask at REFCLK frequency = 312.5 MHz. _{1 MHz}
–
–
–
–123
–
–143
50 MHz
–
–
–145
10 kHz
–
–
–98
CPLL reference clock select phase noise ^{100 kHz}
–
–
–117
mask at REFCLK frequency = 625 MHz. _{1 MHz}
–
–
–140
50 MHz
–
–
–144
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes:
1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
Table 119: GTY Transceiver PLL/Lock Time Adaptation
Symbol
Description
Conditions
T_LOCK
T_DLOCK
Initial PLL lock.
Clock recovery phase acquisition and
adaptation time for decision
feedback equalizer (DFE).
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
After the PLL is locked to
the reference clock, this is
the time it takes to lock
the clock data recovery
(CDR) to the data present
at the input.
All Speed Grades
Min
Typ
Max
–
–
1
–
–
Units
ms
UI
UI
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
93