DS925 Datasheet, PDF (72/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 88: Global Clock Input to Output Delay Without MMCM (Far Clock Region)
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM.
T_{ICKOF_FAR}
Global clock input and output
XCZU2EG
4.69
5.16
5.61
6.13
6.49
ns
flip-flop without MMCM (far clock
region).
XCZU3EG
4.69
5.16
5.61
6.13
6.49
ns
XCZU4EV
ns
XCZU5EV
ns
XCZU6EG
5.62
5.98
6.38
7.39
7.46
ns
XCZU7EV
ns
XCZU9EG
5.62
5.98
6.38
7.39
7.46
ns
XCZU11EG
ns
XCZU15EG 5.69
6.30
6.83
7.60
8.17
ns
XCZU17EG
ns
XCZU19EG
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
Table 89: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
T_ICKOFMMCMCC Global clock input and output
flip-flop with MMCM.
XCZU2EG 2.65
2.72
2.94
3.25
3.32
ns
XCZU3EG 2.65
2.72
2.94
3.25
3.32
ns
XCZU4EV
ns
XCZU5EV
ns
XCZU6EG 2.75
2.82
3.01
3.49
3.49
ns
XCZU7EV
ns
XCZU9EG 2.75
2.82
3.01
3.49
3.49
ns
XCZU11EG
ns
XCZU15EG 2.77
2.82
3.08
3.43
3.53
ns
XCZU17EG
ns
XCZU19EG
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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