DS925 Datasheet, PDF (62/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 78 shows the test setup parameters used for measuring input delay.
Table 78: Input Delay Measurement Methodology
Description
I/O Standard
Attribute
V_L(1)(2)
V_H(1)(2)
(1^V)M(4E)A(S6) (1^V)(R3E)F(5)
LVCMOS, 1.2V
LVCMOS12
0.1
1.1
0.6
–
LVCMOS, LVDCI, HSLVDCI, 1.5V
LVCMOS15,
LVDCI_15,
HSLVDCI_15
0.1
1.4
0.75
–
LVCMOS, LVDCI, HSLVDCI, 1.8V
LVCMOS18,
LVDCI_18,
HSLVDCI_18
0.1
1.7
0.9
–
LVCMOS, 2.5V
LVCMOS25
0.1
2.4
1.25
–
LVCMOS, 3.3V
LVCMOS33
0.1
3.2
1.65
–
LVTTL, 3.3V
LVTTL
0.1
3.2
1.65
–
HSTL (high-speed transceiver logic),
class I, 1.2V
HSTL_I_12
V_REF – 0.5
V_REF + 0.5
V_REF
0.6
HSTL, class I, 1.5V
HSTL_I
HSTL, class I, 1.8V
HSTL_I_18
HSUL (high-speed unterminated logic), 1.2V HSUL_12
SSTL12 (stub series terminated logic), 1.2V SSTL12
SSTL135 and SSTL135 class II, 1.35V
SSTL135,
SSTL135_II
V_REF – 0.65
V_REF – 0.8
V_REF – 0.5
V_REF – 0.5
V_REF + 0.65
V_REF + 0.8
V_REF + 0.5
V_REF + 0.5
V_REF – 0.575 V_REF + 0.575
V_REF
V_REF
V_REF
V_REF
V_REF
0.75
0.9
0.6
0.6
0.675
SSTL15 and SSTL15 class II, 1.5V
SSTL18, class I and II, 1.8V
SSTL15, SSTL15_II
SSTL18_I,
SSTL18_II
V_REF – 0.65
V_REF – 0.8
V_REF + 0.65
V_REF + 0.8
V_REF
V_REF
0.75
0.9
POD10, 1.0V
POD12, 1.2V
DIFF_HSTL, class I, 1.2V
POD10
POD12
DIFF_HSTL_I_12
V_REF – 0.6
V_REF – 0.74
0.6 – 0.125
V_REF + 0.6
V_REF + 0.74
0.6 + 0.125
V_REF
V_REF
0⁽⁶⁾
0.7
0.84
–
DIFF_HSTL, class I, 1.5V
DIFF_HSTL, class I, 1.8V
DIFF_HSUL, 1.2V
DIFF_SSTL, 1.2V
DIFF_HSTL_I
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_HSTL_I_18
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
DIFF_HSUL_12
0.6 – 0.125 0.6 + 0.125
0⁽⁶⁾
–
DIFF_SSTL12
0.6 – 0.125 0.6 + 0.125
0⁽⁶⁾
–
DIFF_SSTL135 and DIFF_SSTL135 class II, DIFF_SSTL135,
1.35V
DIFF_SSTL135_II
0.675 – 0.125 0.675 + 0.125
0⁽⁶⁾
–
DIFF_SSTL15 and DIFF_SSTL15 class II,
1.5V
DIFF_SSTL15,
DIFF_SSTL15_II
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
DIFF_POD10, 1.0V
DIFF_POD10
0.7 – 0.125 0.7 + 0.125
0⁽⁶⁾
–
DIFF_POD12, 1.2V
DIFF_POD12
0.84 – 0.125 0.84 + 0.125 0⁽⁶⁾
–
LVDS (low-voltage differential signaling),
1.8V
LVDS
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
DS925 (v1.1) June 20, 2016
Advance Product Specification
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