DS925 Datasheet, PDF (36/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Table 44: Linear Quad-SPI Interface⁽¹⁾ (Cont’d)
Symbol
Description
Load
Conditions⁽²⁾
Min
Max
Units
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O
standard.
T_DCQSPICLK7 Quad-SPI clock duty cycle.
15 pF
45
55
%
30 pF
45
55
%
T_QSPISSSCLK7 Slave select asserted to next clock edge.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPISCLKSS7 Clock edge to slave select deasserted.
15 pF
7.0
–
ns
30 pF
7.0
–
ns
T_QSPICKO7
Clock to output delay, all outputs.
15 pF
5.2 14.8
ns
30 pF
5.2 14.8
ns
T_QSPIDCK7
Setup time, all inputs.
15 pF
14.0
–
ns
30 pF
14.0
–
ns
T_QSPICKD7
Hold time, all inputs.
15 pF
0.0
–
ns
30 pF
0.0
–
ns
F_QSPIREFCLK7 Quad-SPI reference clock frequency.
15 pF
30 pF
–
160
–
160
MHz
MHz
F_QSPICLK7
Quad-SPI device clock frequency.
15 pF
30 pF
–
40
–
40
MHz
MHz
Notes:
1. The test conditions are configured for the linear Quad-SPI interface at 100 MHz with a 12 mA drive strength and fast slew
rate. The test conditions are configured for the linear Quad-SPI interface at 40 MHz with an 8 mA drive strength and fast
slew rate.
2. 30 pF loads are for stacked modes.
X-Ref Target - Figure 5
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
CPOL = 0
T_{QSPISSCLK{1, 2, 5}}
T_{QSPICLKSS{1, 2, 5}}
T_{QSPISSCLK{1, 2, 5}}
T_{QSPICLKSS{1, 2, 5}}
QSPI_SCLK_OUT
CPOL = 1
T_{QSPICKO{1, 2, 5}}
QSPI{1,0}_IO_[3,0]
OUT0
OUT1
T_{QSPIDCK{1, 2, 5}}
INn-2
T_{QSPICKD{1, 2, 5}}
INn-1
Figure 5: Quad-SPI Interface (Feedback Clock Enabled) Timing
INn
ds925_qspi_en_110515
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
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