DS925 Datasheet, PDF (103/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
Integrated Interface Block for PCI Express Designs
More information and documentation on solutions for PCI Express designs can be found at PCI Express.
The UltraScale Architecture and Product Overview (DS890) lists the Zynq UltraScale+ MPSoCs that include
this block.
Table 132: Maximum Performance for PCI Express Designs⁽¹⁾⁽²⁾
Symbol
Description
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
F_PIPECLK
F_CORECLK
F_DRPCLK
F_MCAPCLK
Pipe clock maximum frequency.
Core clock maximum frequency.
DRP clock maximum frequency.
MCAP clock maximum frequency.
250.00
500.00
250.00
125.00
250.00
500.00
250.00
125.00
250.00
500.00
250.00
125.00
250.00
250.00
250.00
125.00
250.00
250.00
250.00
125.00
Notes:
1. PCI Express Gen4 operation is supported for x1, x2, x4, and x8 widths.
2. PCI Express Gen4 operation is supported in -2I and -3E speed grades.
Units
MHz
MHz
MHz
MHz
Video Codec Performance
The UltraScale Architecture and Product Overview (DS890) lists the Zynq UltraScale+ MPSoC EV devices
that include the Video Codec unit (VCU).
Table 133: VCU Performance
Description
Video Codec decoder block maximum
frequency (H.264/5 10-bit 4:2:2)
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
667
667
667
667
667
Units
MHz
DS925 (v1.1) June 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
103