DS925 Datasheet, PDF (28/109 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
PS NAND Memory Controller Interface
Table 40: ONFI (SDR Mode 5) Switching Characteristics⁽¹⁾
Symbol
Description
Min
Max
Units
T_ONFIALH5
T_ONFIALS5
T_ONFIAR5
T_ONFIADL5
T_ONFICLH5
T_ONFICLR5
T_ONFICLS5
T_ONFICS5
T_ONFICH5
T_ONFIDH5
T_ONFIDS5
T_ONFIRC5
T_ONFIREH5
T_ONFIRHW5
T_ONFIRP5
T_ONFIWC5
T_ONFIWH5
T_ONFIWP5
T_ONFIWB5
T_ONFIWHR5
ALE hold time
ALE setup time
ALE to RE_n delay
Address cycle to data loading time
CLE hold time
CLE to RE_n delay
CLE setup time
CE_n setup time
CE_n hold time
Data hold time
Data setup time
RE_n cycle time
RE_n High hold time
RE_n High to WE_n Low
RE_n pulse width
WE_n cycle time
WE_n High hold time
WE_n pulse width
WE_n to Ready_n Low time
Command, address, or data input cycle to data output cycle
10.2
–
ns
40.6
–
ns
83.3
–
ns
142.8
–
ns
40.9
–
ns
379.0
–
ns
9.8
–
ns
19.8
–
ns
10.7
–
ns
10.1
–
ns
9.9
–
ns
36.0
–
ns
12.0
–
ns
119.3
–
ns
24.0
–
ns
36.0
–
ns
12.0
–
ns
24.0
–
ns
–
100
ns
93.6
–
ns
Notes:
1. The test conditions are configured to the LVCMOS 1.8V I/O standard with a 12 mA drive strength, fast slew rate, and a
15 pF load.
Table 41: ONFI (SDR Mode 0) Switching Characteristics⁽¹⁾
Symbol
Description
T_ONFIALH0
T_ONFIALS0
T_ONFIAR0
T_ONFIADL0
T_ONFICLH0
T_ONFICLR0
T_ONFICLS0
T_ONFICS0
T_ONFICH0
T_ONFIDH0
T_ONFIDS0
T_ONFIRC0
T_ONFIREH0
ALE hold time
ALE setup time
ALE to RE_n delay
Address cycle to data loading time
CLE hold time
CLE to RE_n delay
CLE setup time
CE_n setup time
CE_n hold time
Data hold time
Data setup time
RE_n cycle time
RE_n High hold time
Min
61.3
91.6
144.5
3406.8
20.6
144.0
50.6
70.8
21.0
51.4
50.5
120.0
60.0
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS925 (v1.1) June 20, 2016
Advance Product Specification
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