LAN9303MI-AKZE Datasheet, PDF (97/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
7.2
Port 1 & 2 PHYs
The Port 1 and Port 2 PHYs are functionally identical. The Port 1 PHY is active when Port 1 is
operating in Internal PHY mode. The Port 1 PHY may optionally be bypassed for the connection of an
external MAC or PHY via the Port 1 MII/RMII interface. Each PHY can be divided into the following
functional sections:
„ 100BASE-TX Transmit and 100BASE-TX Receive
„ 10BASE-T Transmit and 10BASE-T Receive
„ PHY Auto-negotiation
„ HP Auto-MDIX
„ MII MAC Interface
„ PHY Management Control
Note 7.1
Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe
them as the “Port x PHY”, or simply “PHY”. Wherever a lowercase “x” has been appended
to a port or signal name, it can be replaced with “1” or “2” to indicate the Port 1 or Port 2
PHY respectively. All references to “PHY” in this section can be used interchangeably for
both the Port 1 & 2 PHYs. This nomenclature excludes the Virtual PHY.
A block diagram of the Port x PHYs main components can be seen in Figure 7.1.
MII
To Port x
Switch Fabric MAC
To MII Mux
MDIO
Auto-
Negotiation
MII
MAC
Interface
PHY Management
Control
Registers
Interrupts
10/100
Transmitter
10/100
Reciever
HP Auto-MDIX
LEDs
PLL
TXPx/TXNx
RXPx/RXNx
To External
Port x Ethernet Pins
To System
Interrupt Controller
To GPIO/LED
Controller
From
System Clocks Controller
Figure 7.1 Port x PHY Block Diagram
SMSC LAN9303M/LAN9303Mi
97
DATASHEET
Revision 1.5 (07-08-11)