LAN9303MI-AKZE Datasheet, PDF (158/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
13.2.2.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
Offset:
1E8h
Size:
32 bits
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into the GPIO Interrupt Event (GPIO) bit of the Interrupt Status Register
(INT_STS). Writing a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a
source. Status bits will still reflect the status of the interrupt source regardless of whether the source
is enabled as an interrupt in this register. The GPIO Interrupt Event Enable (GPIO_EN) bit of the
Interrupt Enable Register (INT_EN) must also be set in order for an actual system level interrupt to
occur. Refer to Chapter 5, "System Interrupts," on page 62 for additional information.
BITS
DESCRIPTION
31:22 RESERVED
21:16
GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
Note:
The GPIO interrupts must also be enabled via the GPIO Interrupt
Event Enable (GPIO_EN) bit of the Interrupt Enable Register
(INT_EN), in order to cause the interrupt pin (IRQ) to be asserted.
15:6 RESERVED
5:0 GPIO Interrupt[5:0] (GPIO[5:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the General Purpose I/O Configuration
Register (GPIO_CFG).
Note: As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 nS to be recognized as interrupt inputs.
TYPE
RO
R/W
RO
R/WC
DEFAULT
-
0h
-
0h
Revision 1.5 (07-08-11)
158
DATASHEET
SMSC LAN9303M/LAN9303Mi